
Analog Integrated Circuit Device Data
Freescale Semiconductor
172
PC34708
Functional Block Requirements and Behaviors
Control Interface SPI/I2C Block Description and Application Information
ADDLY30
8
R/W
DIGRESETB
0
This will allow delay after the set of ADC readings. This delay
is only valid between subsequent wrap around reading
sequences with ADCONT
ADDLY31
9
R/W
DIGRESETB
0
ADDLY32
10
R/W
DIGRESETB
0
ADDLY33
11
R/W
DIGRESETB
0
TSDLY10
12
R/W
DIGRESETB
0
This will allow delay before the ADC Touch screen readings.
This is like the ADDLY1 but allows independent programming
of touchscreen readings from general purpose ADC readings
to prevent code replacement in the system.
TSDLY11
13
R/W
DIGRESETB
0
TSDLY12
14
R/W
DIGRESETB
0
TSDLY13
15
R/W
DIGRESETB
0
TSDLY20
16
R/W
DIGRESETB
0
This will allow delay between each of ADC Touch screen
readings in a set. This is like the ADDLY2 but allows
independent programming of touchscreen readings from
general purpose ADC readings to prevent code replacement
in the system.
TSDLY21
17
R/W
DIGRESETB
0
TSDLY21
18
R/W
DIGRESETB
0
TSDLY23
19
R/W
DIGRESETB
0
TSDLY30
20
R/W
DIGRESETB
0
This will allow delay after the set of ADC Touch screen
readings. This delay is only valid between subsequent wrap
around reading sequences with TSCONT mode. This is like
the ADDLY3 but allows independent programming of
touchscreen readings from general purpose ADC readings to
prevent code replacement in the system.
TSDLY31
21
R/W
DIGRESETB
0
TSDLY31
22
R/W
DIGRESETB
0
TSDLY33
23
R/W
DIGRESETB
0
Table 170. Register 45, ADC 2
Name
Bit #
R/W
Reset
Default
Description
ADSEL00
0
R/W
DIGRESETB
0
Channel Selection to place in ADRESULT0
ADSEL01
1
R/W
DIGRESETB
0
ADSEL02
2
R/W
DIGRESETB
0
ADSEL03
3
R/W
DIGRESETB
0
ADSEL10
4
R/W
DIGRESETB
0
Channel Selection to place in ADRESULT1
ADSEL11
5
R/W
DIGRESETB
0
ADSEL12
6
R/W
DIGRESETB
0
ADSEL13
7
R/W
DIGRESETB
0
ADSEL20
8
R/W
DIGRESETB
0
Channel Selection to place in ADRESULT2
ADSEL21
9
R/W
DIGRESETB
0
ADSEL22
10
R/W
DIGRESETB
0
ADSEL23
11
R/W
DIGRESETB
0
ADSEL30
12
R/W
DIGRESETB
0
Channel Selection to place in ADRESULT3
ADSEL31
13
R/W
DIGRESETB
0
ADSEL32
14
R/W
DIGRESETB
0
ADSEL33
15
R/W
DIGRESETB
0
Table 169. Register 44, ADC 1
Name
Bit #
R/W
Reset
Default
Description