Table of Contents
(Continued)
Revision 1.1
11
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P
9.2.2
9.2.3
Parallel Port Register Map .........................................................................................194
Parallel Port Bitmap Summary ..................................................................................195
9.3
SERIAL PORT 1 (SP1) ............................................................................................................196
9.3.1
General Description ...................................................................................................196
9.3.2
Register Bank Overview ............................................................................................196
9.3.3
SP1 Register Maps ....................................................................................................197
9.3.4
SP1 Bitmap Summary ...............................................................................................199
9.4
SERIAL PORT 2 (SP2) ............................................................................................................200
9.4.1
General Description ...................................................................................................200
9.4.2
Register Bank Overview ............................................................................................200
9.4.3
SP2 Register Map .....................................................................................................202
9.4.4
SP2 Bitmap Summary ...............................................................................................204
9.5
SERIAL PORT 2 (SP2) WITH INFRARED ..............................................................................206
9.5.1
General Description ...................................................................................................206
9.5.2
UART Register Bank Overview .................................................................................206
9.5.3
SP2 Register Map .....................................................................................................207
9.6
KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................210
9.6.1
General Description ...................................................................................................210
9.6.2
KBC Register Map .....................................................................................................211
9.6.3
KBC Bitmap Summary ...............................................................................................211
10.0
Device Characteristics
10.1
GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................212
10.1.1
Recommended Operating Conditions .......................................................................212
10.1.2
Absolute Maximum Ratings .......................................................................................212
10.1.3
Capacitance ..............................................................................................................212
10.1.4
Power Consumption under Recommended Operating Conditions ............................213
10.1.5
Voltage Thresholds ....................................................................................................213
10.2
DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................213
10.2.1
Input, TTL Compatible ...............................................................................................213
10.2.2
Input, TTL Compatible, with Schmitt Trigger .............................................................214
10.2.3
Input, TTL Compatible, with 200 mV Schmitt Trigger ................................................214
10.2.4
Input, TTL Compatible, with 400 mV Schmitt Trigger ................................................214
10.2.5
Input, PCI 3.3V Compatible .......................................................................................215
10.2.6
Input, SMBus Compatible ..........................................................................................215
10.2.7
Analog Input ..............................................................................................................215
10.2.8
Output, TTL/CMOS Compatible, Push-Pull Buffer ....................................................215
10.2.9
Output, TTL/CMOS Compatible, Open-Drain Buffer .................................................216
10.2.10 Output, PCI 3.3V Compatible ....................................................................................216
10.2.11 Analog Output ............................................................................................................216
10.2.12 Input/Output Switch, SMBus Compatible ..................................................................216
10.2.13 Exceptions .................................................................................................................217
10.2.14 Terminology ...............................................................................................................217
10.3
INTERNAL RESISTORS .........................................................................................................218
10.3.1
Pull-Up Resistor .........................................................................................................218
10.3.2
Pull-Down Resistor ....................................................................................................218
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