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4
Revision1.1
P
Revision Record
Revision Date
Status
Comments
March 17, 2003
Draft Revision 0.03
First Draft of Arch. Spec.
April 15, 2003
Draft Revision 0.1
Add Serial InfraRed Port
Update all sections
June 7, 2003
Draft Revision 0.3
Change Clock generator and CLOCKCF register
Add Heceta6 Emulation module and complementing configuration
registers: H6_SMBCF, SIOCFB, and its logical device (LDN=08h)
configuration registers
Define ETC (Enhanced Thermal Control) behavior
Change DC spec of GPIOE10-13
Add IN
TS2
buffer type
Correct LPCPD timing
Correct LPC t
VAL
Rename the following functions:
GPO24 to GPO41, GPIOE25 to GPIOE24,
GPIOE26 to GPIOE25, GPIOE27 to GPIOE26
Change in GPCFG2 register
Correct memory map support for SWC
Typos and clarifications
June 22, 2003
Draft Revision 0.5
Rename Port Angeles 3 to PC87374L
Rename 3V_DDCSCL, 3V_DDCSDA to CC_DDCSCL,
CC_DDCSDA
Support 2.5V SMBus on CC_DDCS
nn
pins
Update Clock Domains Section, changes in CLOCKCF register,
High-Frequency Clock Timing, Low-Frequency Clock Timing
SIOCFB register is changed to be powered by V
BAT
Register 61h for LDN=08h: H6_LPC_EMUL is changed
Hecteta6 Emulation: changed Table 62, changed Tachometer
Reading registers
Changed FMC Registers: FT_CTL, FT_LOW, FT_HYST and
FT_RNG
Change SOUT2 buffer type to O
4/8
Added XOR Tree delay
Update AC spec: V
SB
Power-Up reset, V
DD
Power-Up reset, Main
Power Good, Resume Reset, PS_ON
Add Power Consumption numbers
Add SMBus timing, InfraRed Port timing
Typos and clarifications
August 2, 2003
Draft Revision 0.6
Remove HMC and FMC modules
Remove SCK_BJT_GATE, LPCPD, GPIOE15,
GPIOE26-20, GPIO37-30, GPO41-40 signals
Pins 52, 102, 123 are NC (Not Connected)
Allow multiple pin locations for GPIO signals and rename pins with
GPIOs, change default PU/PD, allow routing of a GPIOE input to a
GPIO output
Removed SIOCFB register
SIOCF4[2:1], CLOCKCF[0] are reserved, change in SIOCF3[1:0],
SIOCF4[5:3]
Change drive capability of GPIOE00 (on pin 118) and GPIOE07
(on pin 128)
Change PWRGD_3V functionality
Rename PC87374L to PC8374L
Rename Heceta 6 Emulation to Health Management
H6_SCL and H6_SDA pins renamed to HMSCL and HMSDA pins,
respectively
V
BAT
pin should be connected to V
SB3
(and not V
SS
), when
battery backup features are unused
LED mode selection is not dependent on V
BAT
existence
Typos and clarifications
Winbond Electronics Corp. Advanced PC Product Center