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6
Revision1.1
P
Table of Contents
Features
.............................................................................................................................................................2
Revision Record
...........................................................................................................................................4
1.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAM .........................................................................................................13
1.2
BUFFER TYPES AND SIGNAL/PIN DIRECTORY ....................................................................15
1.3
PIN MULTIPLEXING .................................................................................................................16
1.4
DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................21
1.4.1
LPC Interface ...............................................................................................................21
1.4.2
Serial Port 1 and Serial Port 2 (UART1 and UART2) ..................................................21
1.4.3
InfraRed Port ...............................................................................................................22
1.4.4
Parallel Port .................................................................................................................22
1.4.5
Floppy Disk Controller (FDC) ......................................................................................23
1.4.6
Keyboard and Mouse Controller (KBC) .......................................................................24
1.4.7
General-Purpose I/O (GPIO) .......................................................................................24
1.4.8
Health Management (HM) ...........................................................................................25
1.4.9
System Wake-Up Control (SWC) ................................................................................25
1.4.10
Clock ............................................................................................................................26
1.4.11
Glue Functions ............................................................................................................26
1.4.12
Configuration Straps and Testing ................................................................................28
1.4.13
Power and Ground ......................................................................................................28
1.5
INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................30
2.0
Power, Reset and Clocks
2.1
POWER .....................................................................................................................................32
2.1.1
Power Planes ..............................................................................................................32
2.1.2
Power States ...............................................................................................................32
2.1.3
Power Connection and Layout Guidelines ..................................................................33
2.2
RESET SOURCES AND TYPES ...............................................................................................34
2.2.1
V
BAT
Power-Up Reset .................................................................................................35
2.2.2
VSB Power-Up Reset ..................................................................................................35
2.2.3
VDD Power-Up Reset ..................................................................................................35
2.2.4
Hardware Reset ...........................................................................................................35
2.2.5
Software Reset ............................................................................................................36
2.3
CLOCK DOMAINS .....................................................................................................................36
2.3.1
LPC Domain ................................................................................................................36
2.3.2
48 MHz Domain ...........................................................................................................36
2.3.3
Standby Domain ..........................................................................................................36
2.4
TESTABILITY SUPPORT ..........................................................................................................37
2.4.1
ICT ...............................................................................................................................37
2.4.2
XOR Tree Testing ........................................................................................................37
3.0
Device Architecture and Configuration
3.1
OVERVIEW ...............................................................................................................................38
3.2
CONFIGURATION STRUCTURE AND ACCESS .....................................................................38
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