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Revision 1.1
P
Features
System Health Support
■
SensorPath
digital/analog partitioning
—
Simplifies board design and routing
—
Supports distributed sensors and centralized control
—
Health monitoring is self-contained and requires
minimal host attention
—
Faster boot time
—
Off loads SMBus, and enables ASF compliance
interface
to
sensors
optimizes
■
Fan Monitor and Control
—
Three PWM-based fan controls
—
Four 16-bit resolution tachometer inputs
—
Software or local temperature feedback control
■
Heceta6-compatible register set accessible via the
LPC interface and SMBus
—
SupportsthefollowingcombinationsofLMxxdevices:
LM96011 and optional LM95010
LM96012
LM96010
—
SimultaneousreadsupportviaLPCinterfaceandSMBus
Glue Functions
■
Generates the power-related signals:
—
Main Power good
—
Power distribution control (for switching between
Main and Standby regulators)
—
Resume reset (Master Reset) according to the 5V
standby supply status
—
Main power supply turn on (PS_ON)
■
Voltage translation between 2.5V or 3.3V levels (DDC) and
5Vlevels(VGA)fortheSMBusserialclockanddatasignals
■
IsolationcircuitryfortheSMBusserialclockanddatasignals
■
Buffers PCI_RESET to generate two reset output signals
■
Buffers PCI_RESET to generate IDE reset output.
■
Generates “highest active supply” reference voltage
—
Based on 3.3V and 5V Main supplies
—
Based on 3.3V and 5V Standby supplies
■
High-current LED driver control for Hard Disk Drive
activity indication
■
Software selectable alternative functionality, through pin
multiplexing
General-Purpose I/O (GPIO) Ports
■
All 16 GPIO ports powered by V
SB3
■
Each pin individually configured as input or output
■
Programmable features for each output pin:
—
Drive type (open-drain, push-pull or TRI-STATE
)
—
TRI-STATE
on
detection
V
SB3
-powered pins driving V
DD
-supplied devices
■
Programmable option for internal pull-up resistor on each
input pin (some with internal pull-down resistor option)
of
falling
V
DD3
for
■
Lockoptionfortheconfigurationanddataofeachoutputpin
■
15 GPIO ports generate IRQ/SIOPME for wake-up
events; each GPIO has separate:
—
Enable control of event status routing to IRQ
—
EnablecontrolofeventstatusroutingtoSIOPME(viaSWC)
—
Polarity and edge/level selection
Programmable debouncing
Power Management
■
Supports
ACPI Specification Revision 2.0b, July 27, 2000
■
System Wake-Up Control (SWC)
—
Optional
routing
(SIOPME) on detection of:
Keyboard or Mouse events
Ring Indication RI on each of the two serial ports
General-Purpose Input Events from 15 GPIO pins
IRQs of the Keyboard and Mouse Controller
IRQs of the other internal modules
—
Optional routing of the SCI (SIOPME) to generate
IRQ (SERIRQ)
—
Implements the GPE1_BLK of the ACPI General Pur-
pose (Generic) Register blocks with “child” events
—
V
SB3
-powered event detection and event-logic
configuration
of
events
to
generate
SCI
■
Enhanced Power Management (PM), including:
—
Special configuration registers for power down
—
Low-leakage pins
—
Low-power CMOS technology
—
Ability to disable all modules
—
High-current LED drivers control (two LEDs) for
power status indication with:
Standard blinking, controlled by software
Advanced blinking, controlled by power supply
status, sleep state or software
Special blinking, controlled by power supply sta-
tus, sleep state and software bit
—
V
BAT
-powered indication of the Main power supply
state before an AC power failure
■
Keyboard Events
—
Wake-up on any key
—
Supports programmable 8-byte sequence “Pass-
word” or “Special Keys” for Power Management
—
Simultaneous recognition of three programmable
keys (sequences): “Power”, “Sleep” and “Resume”
—
Wake-up on mouse movement and/or button click
Bus Interface
■
LPC Bus Interface
—
Based on Intel’s
LPC Interface Specification Revi-
sion 1.1, August 2002
—
I/O, Memory and 8-bit Firmware Memory read and
write cycles
—
Up to four 8-bit DMA channels
—
Serial IRQ (SERIRQ)
—
Supports registers memory and I/O mapping
Winbond Electronics Corp. Advanced PC Product Center