参数资料
型号: PC9RS08KA2PAE
厂商: Freescale Semiconductor
文件页数: 128/136页
文件大小: 0K
描述: MCU 8BIT 2KB FLASH RS08 8-DIP
标准包装: 50
系列: RS08
核心处理器: RS08
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,WDT
输入/输出数: 4
程序存储器容量: 2KB(2K x 8)
程序存储器类型: 闪存
RAM 容量: 63 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
配用: DEMO9RS08KA2-ND - DEMO BOARD FOR 9RS08KA2
Modulo Timer (RS08MTIMV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
91
11.1.3
Block Diagram
The block diagram for the modulo timer module is shown Figure 11-2.
Figure 11-2. Modulo Timer (MTIM) Block Diagram
11.2
External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in Table 11-1.
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter
must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for
the pin location and priority of this function.
11.3
Register Definition
Each MTIM includes four registers, which are summarized in Table 11-2:
An 8-bit status and control register
An 8-bit clock configuration register
An 8-bit counter register
An 8-bit modulo register
Refer to the direct-page register summary in the memory section of this data sheet for the absolute address
assignments for all MTIM registers. This section refers to registers and control bits only by their names.
Table 11-1. Signal Properties
Signal
Function
I/O
TCLK
External clock source input into MTIM
I
BUSCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALEAND
SELECT DIVIDE
BY
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS
PS
XCLK
TOIE
MTIM
INTERRUPT
REQUEST
TOF
8-BIT COUNTER
(MTIMCNT)
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