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| 型号： | PC9S08AC128CLKE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 18/40页 |
| 文件大小： | 0K |
| 描述： | MCU 8BIT 128K FLASH 80-LQFP |
| 标准包装： | 90 |
| 系列： | S08 |
| 核心处理器： | S08 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，LIN，SCI，SPI |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 69 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 托盘 |
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Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
25
3.9.1
ICG Frequency Specifications
Table 3-11. ICG Frequency Specifications
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 5.0V, 25C unless otherwise stated.
Max
Unit
1
Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range
High range
High Gain, FBE (HGO = 1,CLKS = 10)
High Gain, FEE (HGO = 1,CLKS = 11)
Low Power, FBE (HGO = 0, CLKS = 10)
Low Power, FEE (HGO = 0, CLKS = 11)
flo
fhi_byp
fhi_eng
flp_byp
flp_eng
32
1
2
1
2
—
100
16
10
8
kHz
MHz
2
Input clock frequency (CLKS = 11, REFS = 0)
Low range
High range
flo
fhi_eng
32
2
—
100
10
kHz
MHz
3
Input clock frequency (CLKS = 10, REFS = 0)
fExtal
0—
40
MHz
4
Internal reference frequency (untrimmed)
fICGIRCLK
182.25
243
303.75
kHz
5
Duty cycle of input clock (REFS = 0)
tdc
40
—
60
%
6
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
fICGOUT
fExtal (min)
flo (min)
—
fExtal (max)
fICGDCLKmax(
max)
MHz
7
Minimum DCO clock (ICGDCLK) frequency
fICGDCLKmin
3—
MHz
8
Maximum DCO clock (ICGDCLK) frequency
fICGDCLKmax
—40
MHz
9
Self-clock mode (ICGOUT) frequency 2
2 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
fSelf
fICGDCLKmin
fICGDCLKmax
MHz
10
Self-clock mode reset (ICGOUT) frequency
fSelf_reset
5.5
8
10.5
MHz
11
Loss of reference frequency 3
Low range
High range
fLOR
5
50
25
500
kHz
12
Loss of DCO frequency 4
fLOD
0.5
1.5
MHz
13
Crystal start-up time 5, 6
Low range
High range
t
CSTL
t
CSTH
—
430
4
—
ms
14
FLL lock time , 7
Low range
High range
tLockl
tLockh
—
2
ms
15
FLL frequency unlock range
nUnlock
–4*N
4*N
counts
16
FLL frequency lock range
nLock
–2*N
2*N
counts
17
ICGOUT period jitter, , 8 measured at fICGOUT Max
Long term jitter (averaged over 2 ms interval)
CJitter
—0.2
% fICG
18
Internal oscillator deviation from trimmed
frequency9
VDD = 2.7 – 5.5 V, (constant temperature)
VDD = 5.0 V 10%, –40 C to 125C
ACCint
—
0.5
2
%
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