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| 型号： | PC9S08AC128CLKE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | MCU 8BIT 128K FLASH 80-LQFP |
| 标准包装： | 90 |
| 系列： | S08 |
| 核心处理器： | S08 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，LIN，SCI，SPI |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 69 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 托盘 |
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Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
27
3.10
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1
Control Timing
Figure 3-10. Reset Timing
Table 3-12. Control Timing
Num
C
Parameter
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 5.0V, 25C unless otherwise stated.
Max
Unit
1
Bus frequency (tcyc = 1/fBus)fBus
dc
—
20
MHz
2
Real-time interrupt internal oscillator period
tRTI
600
1500
s
External reset pulse width2
(tcyc = 1/fSelf_reset)
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst
1.5 x
tSelf_reset
—ns
4
Reset low drive3
3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
trstdrv
34 x tcyc
—ns
5
Active background debug mode latch setup time
tMSSU
25
—
ns
6
Active background debug mode latch hold time
tMSH
25
—
ns
7
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5 x tcyc
——
ns
8
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
——
ns
9
Port rise and fall time (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40C to 125C.
tRise, tFall
—
3
30
ns
textrst
RESET PIN
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