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参数资料
| 型号： | PC9S08AC128CLKE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/40页 |
| 文件大小： | 0K |
| 描述： | MCU 8BIT 128K FLASH 80-LQFP |
| 标准包装： | 90 |
| 系列： | S08 |
| 核心处理器： | S08 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，LIN，SCI，SPI |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 69 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 托盘 |
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Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
14
Freescale Semiconductor
Solving equations 1 and 2 for K gives:
K = PD (TA + 273C) + JA (PD)
2
Eqn. 3-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
3.6
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 3-4. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human Body
Series Resistance
R1
1500
Storage Capacitance
C
100
pF
Number of Pulse per pin
–
3
Machine
Series Resistance
R1
0
Storage Capacitance
C
200
pF
Number of Pulse per pin
–
3
Latch-up
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Table 3-5. ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
Min
Max
Unit
1
C Human Body Model (HBM)
VHBM
2000
–
V
2
C Machine Model (MM)
VMM
200
–
V
3
C Charge Device Model (CDM)
VCDM
500
–
V
4C Latch-up Current at TA = 125CILAT
100
–
mA
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