参数资料
| 型号： | PCA9500PW,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 25/26页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16TSSOP |
| 产品培训模块： | I²C Bus Fundamentals |
| 特色产品： | NXP - I2C Interface |
| 标准包装： | 96 |
| 接口： | I²C，SM 总线 |
| 输入/输出数： | 8 |
| 中断输出： | 无 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.5 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 包括： | EEPROM，POR |
| 产品目录页面： | 824 (CN2011-ZH PDF) |
| 其它名称： | 568-1025-5 935271534112 PCA9500PW |
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
8 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7.4.1.2
Page write
A page write is initiated in the same way as the byte write. If after sending the rst word of
data, the STOP condition is not received, the PCA9500 considers subsequent words as
data. After each data word the PCA9500 responds with an acknowledge and the two least
signicant bits of the memory address eld are incremented. Should the master not send
a STOP condition after four data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
7.4.2 Read operations
PCA9500 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
7.4.2.1
Current address read
The PCA9500 contains an internal address counter that increments after each read or
write access and as a result, if the last word accessed was at address ‘n’, then the
address counter contains the address ‘n + 1’.
When the PCA9500 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address stored in the address counter. The master ceases the transmission by issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
See Figure 12.
Fig 10. Byte write
0
A
S
slave address (memory)
START condition
R/W
acknowledge
from slave
002aae594
word address
SDA
0
1
0
A2 A1 A0
1
P
STOP condition.
Write to the memory
is performed.
A
acknowledge
from slave
data
A
acknowledge
from slave
Fig 11. Page write
0
A
S
slave address (memory)
START condition
R/W
acknowledge
from slave
002aae595
word address
SDA
0
1
0
A2 A1 A0
1
P
STOP condition.
Write to the memory is performed.
A
acknowledge
from slave
data to memory
A
acknowledge
from slave
DATA n
data to memory
A
acknowledge
from slave
DATA n + 3
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