参数资料
| 型号： | PCA9500PW,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 8/26页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16TSSOP |
| 产品培训模块： | I²C Bus Fundamentals |
| 特色产品： | NXP - I2C Interface |
| 标准包装： | 96 |
| 接口： | I²C，SM 总线 |
| 输入/输出数： | 8 |
| 中断输出： | 无 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.5 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 包括： | EEPROM，POR |
| 产品目录页面： | 824 (CN2011-ZH PDF) |
| 其它名称： | 568-1025-5 935271534112 PCA9500PW |
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
16 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
12. Dynamic characteristics
[1]
All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
[2]
tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specied operation can be initiated. These parameters are
guaranteed by design.
[3]
Tcy(W) is the maximum time that the device requires to perform the internal write operation.
Table 6.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
SCL clock frequency
-
400
kHz
tSP
pulse width of spikes that must be
suppressed by the input lter
-
50
ns
tBUF
bus free time between a STOP and START
condition
1.3
-
s
tSU;STA
set-up time for a repeated START condition
0.6
-
s
tHD;STA
hold time (repeated) START condition
0.6
-
s
tr
rise time of both SDA and SCL signals
-
0.3
s
tf
fall time of both SDA and SCL signals
-
0.3
s
tSU;DAT
data set-up time
250
-
ns
tHD;DAT
data hold time
0
-
ns
tVD;DAT
data valid time
SCL LOW to
data output
-
1.0
s
tSU;STO
set-up time for STOP condition
0.6
-
s
Port timing
tv(Q)
data output valid time
CL ≤ 100 pF
-
4
s
tsu(D)
data input set-up time
CL ≤ 100 pF
0
-
s
th(D)
data input hold time
CL ≤ 100 pF
4
-
s
Power-up timing
tpu(R)
read power-up time
[2] --1
ms
tpu(W)
write power-up time
[2] --5
ms
Write cycle limits (see Figure 23)
Tcy(W)
write cycle time
[3] -
5
10
ms
Table 7.
Non-volatile storage specications
Parameter
Specication
memory cell data retention
10 years minimum
number of memory cell write cycles
100,000 cycles minimum
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