参数资料
型号: PCA9530D,118
厂商: NXP Semiconductors
文件页数: 8/24页
文件大小: 0K
描述: IC LED DRIVER RGB 8-SOIC
产品培训模块: LED Controllers
I²C Bus Fundamentals
标准包装: 1
拓扑: 开路漏极,PWM
输出数: 2
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGB
频率: 400kHz
电源电压: 2.3 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 标准包装
工作温度: -40°C ~ 85°C
产品目录页面: 825 (CN2011-ZH PDF)
其它名称: 568-1830-6
NXP Semiconductors
PCA9530
2-bit I 2 C-bus LED dimmer
7.2 System con?guration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 8 ).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I 2 C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 8.
System con?guration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
002aaa987
PCA9530_3
Fig 9.
Acknowledgement on the I 2 C-bus
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
8 of 24
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