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| 型号： | PCA9624PW,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 10/37页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER RGBA 24-TSSOP |
| 标准包装： | 2,500 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 8 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | RGBA |
| 频率： | 100kHz ~ 1MHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 输出电压： | 40V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
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NXP Semiconductors
PCA9624
8-bit Fm+ I 2 C-bus 100 mA 40 V LED driver
7.3.3 PWM0 to PWM7, individual brightness control
Table 7. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
02h
03h
04h
05h
06h
07h
08h
09h
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
IDC4[7:0]
IDC5[7:0]
IDC6[7:0]
IDC7[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 0000* PWM0 Individual Duty Cycle
0000 0000* PWM1 Individual Duty Cycle
0000 0000* PWM2 Individual Duty Cycle
0000 0000* PWM3 Individual Duty Cycle
0000 0000* PWM4 Individual Duty Cycle
0000 0000* PWM5 Individual Duty Cycle
0000 0000* PWM6 Individual Duty Cycle
0000 0000* PWM7 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
IDCx ? 7 : 0 ?
duty cycle = ---------------------------
256
7.3.4 GRPPWM, group duty cycle control
Table 8. GRPPWM - Group brightness control register (address 0Ah) bit description
Legend: * default value
(1)
Address
0Ah
Register
GRPPWM
Bit
7:0
Symbol
GDC[7:0]
Access
R/W
Value
1111 1111
Description
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC ? 7 : 0 ?
duty cycle = --------------------------
256
(2)
PCA9624
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 September 2012
? NXP B.V. 2012. All rights reserved.
10 of 37
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