参数资料
型号: PCF8576T,118
厂商: NXP Semiconductors
文件页数: 14/44页
文件大小: 0K
描述: IC LCD DVR UNVRSL LOW-MUX 56VSO
标准包装: 500
显示器类型: LCD
配置: 8 段,15 段,160 元件
接口: I²C,2 线串口
数字或字符: 10 字符,20 字符,160 元件
电流 - 电源: 180µA
电源电压: 2 V ~ 9 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-BSOP(0.435",11.50mm 宽)
供应商设备封装: 56-VSOP
包装: 带卷 (TR)
其它名称: 933740730118
PCF8576TD-T
PCF8576TD-T-ND
Philips Semiconductors
Universal LCD driver for low multiplex rates
Product speci?cation
PCF8576
6.5
Oscillator
6.6
Timing
6.5.1
I NTERNAL CLOCK
The timing of the PCF8576 organizes the internal data flow
The internal logic and the LCD drive signals of the
PCF8576 are timed either by the internal oscillator or from
an external clock. When the internal oscillator is used,
pin OSC should be connected to pin V SS . In this event, the
output from pin CLK provides the clock signal for
cascaded PCF8566s in the system.
Where resistor R osc to V SS is present, the internal oscillator
is selected. The relationship between the oscillator
frequency on pin CLK (f clk ) and R osc is shown in Fig.9.
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576s in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 2). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to
pin CLK when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
clk
10 3
f
(kHz)
10 2
max
min
MBE531
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation. The
lower clock frequency has the disadvantage of increasing
the response time when large amounts of display data are
transmitted on the I 2 C-bus.
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I 2 C-bus but no data loss occurs.
Table 2
LCD frame frequencies
NOMINAL
10
10 2
10 3
R osc (k ?)
10 4
PCF8576 MODE
FRAME
FREQUENCY
FRAME
FREQUENCY
(Hz)
? 3.4 × 10 7 ?
f clk ≈ ? ------------------------ ? ( kHz )
? R osc ?
Fig.9 Oscillator frequency as a function of R osc .
Normal mode
Power-saving mode
f clk
-------------
2880
f clk
----------
480
64
64
6.5.2
E XTERNAL CLOCK
6.7
Display latch
The condition for external clock is made by connecting
pin OSC to pin V DD ; pin CLK then becomes the external
clock input.
The clock frequency (f clk ) determines the LCD frame
frequency and the maximum rate for data reception from
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
the I 2 C-bus. To allow I 2 C-bus transmissions at their
maximum data rate of 100 kHz, f clk should be chosen to be
6.8
Shift register
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
2001 Oct 02
14
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
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