参数资料
| 型号： | PCF8576T,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 19/44页 |
| 文件大小： | 0K |
| 描述： | IC LCD DVR UNVRSL LOW-MUX 56VSO |
| 标准包装： | 500 |
| 显示器类型： | LCD |
| 配置： | 8 段，15 段，160 元件 |
| 接口： | I²C，2 线串口 |
| 数字或字符： | 10 字符，20 字符，160 元件 |
| 电流 - 电源： | 180µA |
| 电源电压： | 2 V ~ 9 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSOP（0.435"，11.50mm 宽） |
| 供应商设备封装： | 56-VSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 933740730118 PCF8576TD-T PCF8576TD-T-ND |
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Philips Semiconductors
Universal LCD driver for low multiplex rates
Product speci?cation
PCF8576
7
CHARACTERISTICS OF THE I 2 C-BUS
7.5
PCF8576 I 2 C-bus controller
The I 2 C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
The PCF8576 acts as an I 2 C-bus slave receiver. It does
not initiate I 2 C-bus transfers or transmit data to an I 2 C-bus
master receiver. The only data output from the PCF8576
are the acknowledge signals of the selected devices.
Device selection depends on the I 2 C-bus slave address,
on the transferred command data and on the hardware
subaddress.
7.1
Bit transfer (see Fig.12)
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally connected to V SS which
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal.
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are connected to V SS or V DD in
accordance with a binary coding scheme such that no two
devices with a common I 2 C-bus slave address have the
same hardware subaddress.
7.2
START and STOP conditions (see Fig.13)
In the power-saving mode it is possible that the PCF8576
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P).
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576 forces the SCL line to LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I 2 C-bus and
serves to slow down fast transmitters. Data loss does not
7.3
System con?guration (see Fig.14)
occur.
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
7.6
Input ?lters
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.4
Acknowledge (see Fig.15)
The number of data bytes transferred between the START
7.7
I 2 C-bus protocol
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
2001 Oct 02
19
Two I 2 C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576. The least significant bit of the
slave address that a PCF8576 will respond to is defined by
the level connected at its input pin SA0. Therefore, two
types of PCF8576 can be distinguished on the same
I 2 C-bus which allows:
? Up to 16 PCF8576s on the same I 2 C-bus for very large
LCD applications
? The use of two types of LCD multiplex on the same
I 2 C-bus.
The I 2 C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I 2 C-bus
master which is followed by one of the two PCF8576 slave
addresses available. All PCF8576s with the corresponding
SA0 level acknowledge in parallel with the slave address
but all PCF8576s with the alternative SA0 level ignore the
whole I 2 C-bus transfer.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCF8576TD | 功能描述:LCD 驱动器 LCD DVR UNVRSL LOW-MUX RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| PCF8576TD-T | 功能描述:LCD 驱动器 160 SEGMENT LCD SEGMENT DRIVER RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| PCF8576U | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF8576U/10 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF8576U/12 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
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