FALC
56
PEF 2256 H/E
Signaling Controller Operating Modes
User’s Manual
Hardware Description
219
DS1.1, 2003-10-23
defined by register XC0.SA8E to SA84E and the corresponding bits of
TSWM.TSA(8:4). Any combination of S
a
-bits can be selected. After the data has
been sent out completely an “all ones” or Flags (CCR1.ITF) is transmitted. The
continuous transmission of a transparent bit stream, which is stored in the XFIFO,
can be enabled.
With the setting of bit MODE.HRAC the received S
a
-bits can be forwarded to the
receive FIFO.
The access to and from the FIFOs is supported by ISR0.RME/RPF and ISR1.XPR/
ALS.
8.3.7
The FALC
56 supports signaling and maintenance functions for T1/J1 primary rate
Interfaces using the Extended Super Frame format. The HDLC channel 1 of the device
supports the DL-channel protocol for ESF format according to T1.403-1989 ANSI or to
AT&T TR54016 specification. The HDLC and Bit Oriented Message (BOM) -Receiver
can be switched on/off independently. If the FALC
56 is used for HDLC formats only, the
BOM receiver has to be switched off. If HDLC and BOM receiver has been switched on
(MODE.HRAC/BRAC), an automatic switching between HDLC and BOM mode is
enabled. Storing of received DL-bit information in the RFIFO of the signaling controller
and transmitting the XFIFO contents in the DL-bit positions is enabled by CCR1.EDLX/
EITS = 10. After hardware-reset (pin RES low) or software-reset (CMDR.RRES = 1) the
FALC
56 operates in HDLC mode. If eight or more consecutive ones are detected, the
BOM mode is entered. Upon detection of a flag in the data stream, the FALC
56
switches back to HDLC mode. Operating in BOM mode, the FALC
56 is able to receive
an HDLC frame immediately, i.e. without any preceding flags.
In BOM mode, the following byte format is assumed (the left most bit is received first;
111111110xxxxxx0).
The FALC
56 uses the FF
H
byte for synchronization, the next byte is stored in RFIFO
(first bit received: LSB) if it starts and ends with a “0”. Bytes starting and ending with a
“1” are not stored. If there are no 8 consecutive ones detected within 32 bits, an interrupt
is generated. However, byte sampling is not stopped.
Bit Oriented Message Mode (T1/J1)