![](http://datasheet.mmic.net.cn/330000/PEF2256_datasheet_16444063/PEF2256_84.png)
FALC
56
PEF 2256 H/E
Functional Description E1
User’s Manual
Hardware Description
84
DS1.1, 2003-10-23
4.2.2.1
Transmit Transparent Modes
In transmit direction, contents of time slot 0 frame alignment signal of the outgoing PCM
frame are normally generated by the FALC
56. However, transparency for the complete
time slot 0 can be achieved by selecting the transparent mode XSP.TT0. With the
Transparent Service Word Mask register TSWM the S
i
-bits, A-bit and the S
a
-bits can be
selectively switched through transparently.
Table 18
Enabled by
4.2.2.2
Synchronization Procedure
Synchronization status is reported by bit FRS0.LFA. Framing errors are counted by the
Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4
consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0
in time slot 0 of every other frame not containing the frame alignment word), the selection
is done by bit RC0.ASY4. Additionally, the service word condition can be disabled. When
the framer lost its synchronization an interrupt status bit ISR2.LFA is generated.
In asynchronous state, counting of framing errors and detection of remote alarm is
stopped. AIS is automatically sent to the backplane interface (can be disabled by bit
FMR2.DAIS).
Further on the updating of the registers RSW, RSP, RSA(8:4), RSA6S and RS(16:1) is
halted (remote alarm indication, S
a
/S
i
-Bit access).
The resynchronization procedure starts automatically after reaching the asynchronous
state. Additionally, it can be invoked user controlled by bit FMR0.FRS (force
resynchronization, the FAS word detection is interrupted until the framer is in the
asynchronous state. After that, resynchronization starts automatically).
Synchronous state is established after detecting:
A correct FAS word in frame n,
Transmit Transparent Mode (Doubleframe E1)
Transmit Transparent Source for
Framing
A-Bit
(int. gen.)
via pin XDI
1)
(int. gen.)
(int. gen.)
(int. gen.)
(int. gen.)
XSW.XRA
S
a
-Bits
XSW.XY0…4
3)
S
i
-Bits
XSW.XSIS, XSP.XSIF
via pin XDI
via pin XDI
via pin XDI
XSW.XSIS, XSP.XSIF
XSW.XSIS, XSP.XSIF
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA(8:4)
1)
pin XDI or XSIG or XFIFO buffer (signaling controller)
Additionally, automatic transmission of the A-bit is selectable.
As a special extension for double frame format, the S
a
-bit register can be used optionally.
XSW.XRA
2)
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
2)
via pin XDI
XSW.XY0…4
XSW.XY0…4
XSW.XY0…4
via pin XDI
3)