参数资料
型号: PF38F3050L0YUQ3A
厂商: INTEL CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封装: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件页数: 2/70页
文件大小: 1193K
代理商: PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
10
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
1.2
Acronyms
1.3
Conventions
APS
Automatic Power Savings
EFA
Extended Flash Array
BCR
(PSRAM) Bus Control Register
Buffered EFP
Buffered Enhanced Factory Programming
CR
(Flash) Configuration Register
CSP
Chip Scale Package
MLC
Multi-Level Cell
OTP
One-Time Programmable
PLR
Protection Lock Register
PR
Protection Register
RCR
(PSRAM) Refresh Control Register
RFU
Reserved for Future Use
RWW / RWE
Read-While-Write / Read-While-Erase
SR
Status Register
WSM
Write State Machine
A5
Denotes one element of a signal group, in this case address bit 5.
Clear
Logical zero (0).
DQ[15:0]
Denotes a group of similarly named signals, such as data bus.
F-CE#
Denotes Chip Enable of the flash die, where “F” to denote the
specific signal suffix and “CE#” is the root signal name of the NOR
flash die.
P-CE# or
P-CS#
Denotes Chip Enable of the PSRAM die, where “P” to denote the
specific signal suffix and “CE# or CS#” are the root signal name of
the PSRAM die. PSRAM CE# and CS# is used interchangably
throughout the document.
S-CS1#
Denotes Chip Enable of the SRAM die, where “S” to denote the
specific signal suffix and “CS1#” is the root signal name of the
SRAM die.
Set
Logical one (1).
SR4
A flash status register bit, in this case status register bit 4 of
SR[15:0].
VCC
Signal or voltage connection.
VCC
Signal or voltage level.
VSS
Denotes a global power signal of the stacked device. VSS is common
to all memory dies within a stacked memory device.
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