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| 型号： | PF38F3050L0YUQ3A |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件页数： | 6/70页 |
| 文件大小： | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
14
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
2.3
Device Operation Overview
The following sections describes the bus operations and device state between the flash
and synchronous PSRAM. Bus operations for the L18 stacked device involve the control
of flash and PRAM inputs. The bus operations are shown in Table 2.
Note:
See the Intel StrataFlash Wireless Memory (L18 SCSP) Discrete Datasheet (order
number: Non-Mux I/O doc #251902 and ADMux I/O doc #313295) for complete
descriptions of the flash modes and commands, command bus-cycle definitions, and
flowcharts that illustrate operational routines not documented in this Datasheet.
Notes:
1.
For flash, do not simultaneously assert F-OE# and F-WE#. For PSRAM, do not simultaneously assert
R-OE# and R-WE#.
2.
X can be VIL or VIH for flash or xRAM inputs; VPPLK, VPPL,or VPPH for F-VPP.
3.
Refer to the latest revision of the Intel StrataFlash Wireless Memory (L18 SCSP) Datasheet (order
number:
Non-Mux I/O doc #251902 and ADMux I/O doc #313295) for valid DIN during Flash writes.
4.
Flash CFI query and Status Register accesses, use DQ[7:0] only. All other reads use DQ[15:0].
5.
P-CRE# is low if PSRAM is in standby. P-CRE# is X if PSRAM is in Low-Power mode. See Section 12.0,
“PSRAM Device Operation” on page 54 for more details about Standby and Low Power mode.
6.
WAIT indicates data validity only when in Synchronous mode. Ignore this setting in Asynchronous and
Page-mode.
7.
The Flash and Synchronous PSRAM dies share the WAIT signal.
8.
During AD-Mux I/O operation, ADV# must remain deasserted during the data phase.
Table 2.
Flash and PSRAM Device Bus Operations
De
vic
e
Mode
F-R
ST
#
F-C
E#
F-O
E#
F-W
E#
AD
V#
8
F-V
PP
P-
CR
E#
P-
CS
#
R-
OE
#
R-
WE
#
R-
UB
#,
R-
LB
# DQ[15:0] WAIT7 Notes
Fla
sh
(#
1,
#2
,o
r#
3)
Synchronous
Array and Non-
Array Read
HL
L
H
L
X
X H XX
X
Flash DOUT
Active
1,2,4
Asynchronous
Read
H
L
H XXX H X
X
Flash D
OUT
Deasserted 1,2,4
Write
H
L
H
L
V
PPL
or
VPPH
XH X
X
Flash DIN Deasserted 1,2,3
Output Disable H
L
H H X
X
Any PSRAM mode allowed
Flash
High-Z
Flash
High-Z
1,2
Standby
H H X
X X
X
Flash
High-Z
Flash
High-Z
1,2
Reset
L
XX
X
Flash
High-Z
Flash
High-Z
1,2
PS
RA
M
(#
1o
r#
2)
Read
X H X
X X
X
L
H
L
PSRAM
D
OUT
Active
1,2,5,7
Write
X H X
X X
X
L
H
L
PSRAM DIN
Active
1,2,5,7
Output Disable
Any Flash mode allowed
LL
H H
X
PSRAM
High-Z
PSRAM
High-Z
1,2
Standby
L
H X
X
PSRAM
High-Z
PSRAM
High-Z
1,2
Low Power
Mode
XX XX
X
PSRAM
High-Z
PSRAM
High-Z
1,2
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