参数资料
型号: PH28F256L18T85
厂商: INTEL CORP
元件分类: PROM
英文描述: StrataFlash Wireless Memory
中文描述: 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79
封装: 0.75 MM PITCH, LEAD FREE, VFBGA-79
文件页数: 101/106页
文件大小: 1272K
代理商: PH28F256L18T85
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
101
Table 30.
Partition Region 2 Information
Offset
(1)
P = 10Ah
Bottom
(P+3A)h
(P+3B)h
(P+3C)h
See table below
Address
Len
Bot
2
144:
145:
1
146:
Description
Top
(P+32)h Number of identical partitions within the partition region
(P+33)h
(P+34)h
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(Optional flash features and commands)
Top
13C:
13D:
13E:
(P+3D)h
(P+35)h
1
147:
13F:
(P+3E)h
(P+36)h
1
148:
140:
(P+3F)h
(P+37)h
1
149:
141:
(P+40)h
(P+41)h
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+38)h Partition Region 2 Erase Block Type 1 Information
(P+39)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
(P+3A)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3B)h
(P+3C)h Partition 2 (Erase block Type 1)
(P+3D)h Minimum block erase cycles x 1000
(P+3E)h
Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
4
14A:
14B:
14C:
14D:
14E:
14F:
150:
142:
143:
144:
145:
146:
147:
148:
2
1
(P+47)h
(P+3F)h
1
151:
149:
(P+40)h Partition Region 2 Erase Block Type 2 Information
(P+41)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
(P+42)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+43)h
(P+44)h Partition 2 (Erase block Type 2)
(P+45)h Minimum block erase cycles x 1000
(P+46)h
Partition 2 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 2 (erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
4
14A:
14B:
14C:
14D:
14E:
14F:
150:
2
1
(P+47)h
1
151:
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
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