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参数资料
| 型号： | PHD11N06LT |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | JFETs |
| 英文描述： | N-channel TrenchMOS transistor Logic level FET(N沟道TrenchMOS 晶体管逻辑电平场效应管) |
| 中文描述： | 10.3 A, 55 V, 0.15 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封装： | PLASTIC, DPAK-3 |
| 文件页数： | 6/12页 |
| 文件大小： | 112K |
| 代理商： | PHD11N06LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHP11N06LT, PHB11N06LT
PHD11N06LT
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
) versus avalanche time (t
AV
);
unclamped inductive load
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 10A
Tj = 25 C
VDD = 11 V
VDD = 44 V
0.1
1
10
100
0.001
0.01
0.1
1
10
Avalanche time, t
AV
(ms)
Maximum Avalanche Current, I
AS
(A)
Tj prior to avalanche = 150 C
25 C
0
1
2
3
4
5
6
7
8
9
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
August 1999
6
Rev 1.000
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