参数资料
| 型号： | PI7C8140AMAE |
| 厂商： | Pericom |
| 文件页数： | 43/82页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 标准包装： | 39 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-QFP（14x20） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 48 of 82
March 20, 2007 – Revision 1.01
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
The bridge is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
The bridge detects a data parity error on the primary bus or detects S_PERR# asserted during the
completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 5-5. Assertion of P_PERR#
P_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0 (asserted)
Read
Upstream
Primary
1 / x
1
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
1 / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
1 / x
0
2
Delayed Write
Downstream
Secondary
1 / 1
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
The bridge is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
Bridge detects a data parity error on the secondary bus or detects P_PERR# asserted during the
completion phase of an upstream delayed write transaction on the target (primary) bus.
Table 5-6. Assertion of S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
0
2
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
07-0067
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|---|---|
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