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| 型号： | PIC12C508AT-04/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 49/113页 |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 512X12 8SOIC |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 3,300 |
| 系列： | PIC® 12C |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 4MHz |
| 外围设备： | POR，WDT |
| 输入/输出数： | 5 |
| 程序存储器容量： | 768B（512 x 12） |
| 程序存储器类型： | OTP |
| RAM 容量： | 25 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 配用： | 309-1046-ND - ADAPTER 8-SOIC TO 8-DIP 309-1045-ND - ADAPTER 8-SOIC TO 8-DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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PIC12C5XX
DS40139E-page 40
1999 Microchip Technology Inc.
8.3.1
MCLR ENABLE
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a GPIO. See
MCLR, the internal pull-up is always on.
FIGURE 8-7:
MCLR SELECT
8.4
Power-On Reset (POR)
The PIC12C5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor.
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Electrical Specifications for
details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8.
GP3/MCLR/VPP
MCLRE
INTERNAL MCLR
WEAK
PULL-UP
The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR is held low is
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 8-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be GP3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 8-
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and VDD) actually
reach their full value, is too long. In this situation, when
the start-up timer times out, VDD has not reached the
VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).
For additional information refer to Application Notes
“
Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
Note:
When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, tempera-
ture, etc.) must be meet to ensure opera-
tion. If these conditions are not met, the
device must be held in reset until the oper-
ating conditions are met.
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