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参数资料
| 型号： | PIC16F1508T-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 44/123页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 7KB FLASH 20-SSOP |
| 标准包装： | 1,600 |
| 系列： | PIC® XLP™ 16F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | I²C，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 17 |
| 程序存储器容量： | 7KB（4K x 14） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 数据转换器： | A/D 12x10b，D/A 1x5b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
KSZ8873MLLJ
September 2011
27
M9999-091911-1.8
Switching Engine
The KSZ8873MLLJ features a high-performance switching engine to move data to and from the MACs’ packet buffers. It
operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There are a total
of 256 buffers available. Each buffer is sized at 128 bytes.
MAC Operation
The KSZ8873MLLJ strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
Back-Off Algorithm
The KSZ8873MLLJ implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional
"aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration for
register 4 (0x04) bit [3].
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Illegal Frames
The KSZ8873MLLJ discards frames less than 64 bytes, and can be programmed to accept frames up to1518 bytes, 1536
bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since the KSZ8873MLLJ
supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Full Duplex Flow Control
The KSZ8873MLLJ supports standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8873MLLJ receives a pause control frame, the KSZ8873MLLJ will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it
is flow controlled), only flow control packets from the KSZ8873MLLJ are transmitted.
On the transmit side, the KSZ8873MLLJ has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources, including available buffers, available transmit queues and
available receive queues.
The KSZ8873MLLJ will flow control a port that has just received a packet if the destination port resource is busy. The
KSZ8873MLLJ issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x
standard. Once the resource is freed up, the KSZ8873MLLJ sends out the other flow control frame (XON) with zero pause
time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow
control mechanism from being constantly activated and deactivated.
The KSZ8873MLLJ flow controls all ports if the receive queue becomes full.
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as full duplex flow control. If backpressure is required, the KSZ8873MLLJ sends preambles to
defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8873MLLJ
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet
reception.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC16F1509-E/ML | 功能描述:8位微控制器 -MCU 14KB FLASH 512B RAM 18 I/O 10-BIT ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F1509-E/P | 功能描述:8位微控制器 -MCU 14KB FLASH 512B RAM 18 I/O 10-BIT ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F1509-E/SO | 功能描述:8位微控制器 -MCU 14KB FLASH 512B RAM 18 I/O 10-BIT ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F1509-E/SS | 功能描述:8位微控制器 -MCU 14KB FLASH 512B RAM 18 I/O 10-BIT ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16F1509-I/ML | 功能描述:8位微控制器 -MCU 14KB FLASH 512B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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