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参数资料
型号： PIC16F1508T-I/SS
厂商： Microchip Technology
文件页数： 45/123页
文件大小： 0K
描述： IC MCU 8BIT 7KB FLASH 20-SSOP
标准包装： 1,600
系列： PIC® XLP™ 16F
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
连通性： I²C，LIN，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 17
程序存储器容量： 7KB（4K x 14）
程序存储器类型： 闪存
RAM 容量： 256 x 8
电压 - 电源 (Vcc/Vdd)： 2.3 V ~ 5.5 V
数据转换器： A/D 12x10b，D/A 1x5b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 20-SSOP（0.209"，5.30mm 宽）
包装： 带卷 (TR)
Micrel, Inc.
KSZ8873MLLJ
September 2011
28
M9999-091911-1.8
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
1. Aggressive back-off (register 3 (0x03), bit [0])
2. No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8873MLLJ has an intelligent option to protect the switch system from receiving too many broadcast packets. As
the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources
(bandwidth and available space in transmit queues) may be utilized. The KSZ8873MLLJ has the option to include
“multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled
or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT. At the
beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes
during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99
decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of
preamble between two packets.
Port Individual MAC address and Source Port Filtering
The KSZ8873MLLJ provide individual MAC address for port 1 and port 2 respectively. They can be set at register 142-147
and 148-153. With this feature, the CPU connected to the port 3 can receive the packets from two internet subnets which
has their own MAC address.
The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and 37
bit 6 is set to 1 respectively. For example, the packet will be dropped after it completes the loop of a ring network.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by the KSZ8873 MLLJ is connected to the
device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception.
The following table describes the signals used by the MII bus.
PHY-Mode Connections
MAC-Mode Connections
External MAC
Controller Signals
KSZ8873 MLLJ
PHY Signals
Pin
Descriptions
External
PHY Signals
KSZ8873 MLLJ
MAC Signals
MTXEN
SMTXEN3
Transmit enable
MTXEN
SMRXDV3
MTXER
SMTXER3
Transmit error
MTXER
(not used)
MTXD3
SMTXD33
Transmit data bit 3
MTXD3
SMRXD33
MTXD2
SMTXD32
Transmit data bit 2
MTXD2
SMRXD32
MTXD1
SMTXD31
Transmit data bit 1
MTXD1
SMRXD31
MTXD0
SMTXD30
Transmit data bit 0
MTXD0
SMRXD30
MTXC
SMTXC3
Transmit clock
MTXC
SMRXC3
MCOL
SCOL3
Collision detection
MCOL
SCOL3
MCRS
SCRS3
Carrier sense
MCRS
SCRS3
MRXDV
SMRXDV3
Receive data valid
MRXDV
SMTXEN3
MRXER
(not used)
Receive error
MRXER
SMTXER3
MRXD3
SMRXD33
Receive data bit 3
MRXD3
SMTXD33
MRXD2
SMRXD32
Receive data bit 2
MRXD2
SMTXD32
MRXD1
SMRXD31
Receive data bit 1
MRXD1
SMTXD31
MRXD0
SMRXD30
Receive data bit 0
MRXD0
SMTXD30
MRXC
SMRXC3
Receive clock
MRXC
SMTXC3
Table 3. MII Signals
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