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参数资料
型号： PIC16F526T-I/SL
厂商： Microchip Technology
文件页数： 92/122页
文件大小： 0K
描述： IC PIC MCU FLASH 1KX12 14SOIC
标准包装： 2,600
系列： PIC® 16F
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： POR，WDT
输入/输出数： 11
程序存储器容量： 1.5KB（1K x 12）
程序存储器类型： 闪存
RAM 容量： 67 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 3x8b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 14-SOIC（0.154"，3.90mm 宽）
包装： 带卷 (TR)
配用： ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
其它名称： PIC16F526T-I/SLTR
2009 Microchip Technology Inc.
DS39689F-page 71
PIC18F2221/2321/4221/4321 FAMILY
SPBRGH
EUSART Baud Rate Generator Register High Byte
0000 0000
57, 216
SPBRG
EUSART Baud Rate Generator Register Low Byte
0000 0000
57, 216
RCREG
EUSART Receive Register
0000 0000
57, 224
TXREG
EUSART Transmit Register
0000 0000
57, 221
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
57, 212
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
57, 213
EEADR
EEPROM Address Register
0000 0000 57, 80, 89
EEDATA
EEPROM Data Register
0000 0000 57, 80, 89
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 57, 80, 89
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 57, 81, 90
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
11-1 1111
58, 107
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
00-0 0000
58, 103
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
00-0 0000
58, 105
IPR1
PSPIP(2)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
58, 106
PIR1
PSPIF(2)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
58, 102
PIE1
PSPIE(2)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
58, 104
OSCTUNE
INTSRC
PLLEN(3)
—
TUN4
TUN3
TUN2
TUN1
TUN0
00-0 0000
33, 58
TRISE(2)
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111
58, 124
TRISD(2)
PORTD Data Direction Control Register
1111 1111
58, 120
TRISC
PORTC Data Direction Control Register
1111 1111
58, 117
TRISB
PORTB Data Direction Control Register
1111 1111
58, 114
TRISA
TRISA7(5)
TRISA6(5)
PORTA Data Direction Control Register
1111 1111
58, 111
LATE(2)
—
PORTE Data Latch Register
(Read and Write to Data Latch)
---- -xxx
58, 123
LATD(2)
PORTD Data Latch Register (Read and Write to Data Latch)
xxxx xxxx
58, 120
LATC
PORTC Data Latch Register (Read and Write to Data Latch)
xxxx xxxx
58, 117
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
xxxx xxxx
58, 114
LATA
LATA7(5)
LATA6(5)
PORTA Data Latch Register (Read and Write to Data Latch)
xxxx xxxx
58, 111
PORTE
—
—RE3(4)
RE2(2)
RE1(2)
RE0(2)
---- xxxx
58, 123
PORTD(2)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
58, 120
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
58, 117
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
58, 114
PORTA
RA7(5)
RA6(5)
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000
58, 111
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Legend:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note
1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
2:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3:
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
INTOSC Modes”.
4:
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
5:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6:
Bit 7 and bit 6 are cleared by user software or by a POR.
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