参数资料
型号: PIC16LF1824-E/ML
厂商: Microchip Technology
文件页数: 68/101页
文件大小: 0K
描述: IC MCU 8BIT 7KB FLASH 16QFN
标准包装: 91
系列: PIC® XLP™ mTouch™ 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 32MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 11
程序存储器容量: 7KB(4K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
209
2552K–AVR–04/11
ATmega329/3290/649/6490
21.3
Register Description
21.3.1
ADCSRB – ADC Control and Status Register B
Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
21.3.2
ACSR – Analog Comparator Control and Status Register
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-
ator. When the bandgap reference is used as input to the analog comparator, it will take a
certain time for the voltage to stabilize. If not stabilized, the the first converison may give a wrong
Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Bit
7
654
3210
ACME
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R/W
Initial Value
0
000
0000
Bit
765
4321
0
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
Initial Value
0
N/A
0000
0
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