参数资料
型号: PIC18F448-E/P
厂商: Microchip Technology
文件页数: 5/116页
文件大小: 0K
描述: IC MCU FLASH 8KX16 W/CAN 40-DIP
产品培训模块: Asynchronous Stimulus
标准包装: 10
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
PIC18FXX8
DS41159E-page 100
2006 Microchip Technology Inc.
9.3
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
EXAMPLE 9-3:
INITIALIZING PORTC
FIGURE 9-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISC
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
Peripheral Out Select
Data Bus
WR LATC
WR TRISC
Data Latch
TRIS Latch
RD TRISC
Q
D
Q
CK
QD
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
VDD
VSS
RD PORTC
Peripheral Data In
I/O pin(1)
or
WR PORTC
RD LATC
Schmitt
Trigger
Note
1: I/O pins have diode protection to VDD and VSS.
TRIS
Override
Peripheral Enable
TRIS OVERRIDE
Pin
Override
Peripheral
RC0
Yes
Timer1 Oscillator
for Timer1/Timer3
RC1
Yes
Timer1 Oscillator
for Timer1/Timer3
RC2
No
RC3
Yes
SPI/I2C
Master Clock
RC4
Yes
I2C Data Out
RC5
Yes
SPI Data Out
RC6
Yes
USART Async
Xmit, Sync Clock
RC7
Yes
USART Sync Data
Out
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