参数资料
型号: PIC18F448-E/P
厂商: Microchip Technology
文件页数: 64/116页
文件大小: 0K
描述: IC MCU FLASH 8KX16 W/CAN 40-DIP
产品培训模块: Asynchronous Stimulus
标准包装: 10
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
2006 Microchip Technology Inc.
DS41159E-page 49
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
Page:
TOSU
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
STKPTR
STKFUL
STKUNF
Return Stack Pointer
00-0 0000
PCLATU
—bit 21(2)
Holding Register for PC<20:16>
---0 0000
PCLATH
Holding Register for PC<15:8>
0000 0000
PCL
PC Low Byte (PC<7:0>)
0000 0000
TBLPTRU
—bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
PRODH
Product Register High Byte
xxxx xxxx
PRODL
Product Register Low Byte
xxxx xxxx
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
INTCON2
RBPU
INTEDG0
INTEDG1
—TMR0IP
—RBIP
111- -1-1
INTCON3
INT2IP
INT1IP
—INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
FSR0H
Indirect Data Memory Address Pointer 0 High
---- xxxx
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
N/A
FSR1H
Indirect Data Memory Address Pointer 1 High
---- xxxx
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
BSR
Bank Select Register
---- 0000
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
N/A
FSR2H
Indirect Data Memory Address Pointer 2 High
---- xxxx
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
STATUS
—N
OV
Z
DC
C
---x xxxx
TMR0H
Timer0 Register High Byte
0000 0000
TMR0L
Timer0 Register Low Byte
xxxx xxxx
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
OSCCON
—SCS
---- ---0
LVDCON
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
WDTCON
—SWDTEN
---- ---0
RCON
IPEN
—RI
TO
PD
POR
BOR
0--1 110q
31, 58, 91
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note
1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
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