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| 型号： | PIC18F85J50T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 32/61页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 16KX16 80TQFP |
| 产品培训模块： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 标准包装： | 1,200 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 48MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART，USB |
| 外围设备： | 欠压检测/复位，LVD，POR，PWM，WDT |
| 输入/输出数： | 65 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 3.8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 12x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-TQFP |
| 包装： | 带卷 (TR) |
| 配用： | AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84 MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB AC164328-ND - MODULE SKT FOR 80TQFP |
| 其它名称： | PIC18F85J50T-I/PTTR |
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Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
35
Serial Port Control Register (SCON)
The serial port control and status register is the Special Function
Register SCON, shown in Figure 30. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
The Framing Error bit (FE) allows detection of missing stop bits in
the received data stream. The FE bit shares the bit position SCON.7
with the SM0 bit. Which bit appears in SCON at any particular time
is determined by the SMOD0 bit in the PCON register. If SMOD0 =
0, SCON.7 is the SM0 bit. If SMOD0 = 1, SCON.7 is the FE bit.
Once set, the FE bit remains set until it is cleared by software. This
allows detection of framing errors for a group of characters without
the need for monitoring it for every character individually.
BIT
SYMBOL
FUNCTION
SCON.7
FE
Framing Error. This bit is set by the UART receiver when an invalid stop bit is detected. Must be
cleared by software. The SMOD0 bit in the PCON register must be 1 for this bit to be accessible.
See SM0 bit below.
SCON.7
SM0
With SM1, defines the serial port mode. The SMOD0 bit in the PCON register must be 0 for this bit
to be accessible. See FE bit above.
SCON. 6
SM1
With SM0, defines the serial port mode (see table below).
SM0, SM1
UART Mode
Baud Rate
0 0
0: shift register
CPU clock/6
0 1
1: 8-bit UART
Variable (see text)
1 0
2: 9-bit UART
CPU clock/32 or CPU clock/16
1 1
3: 9-bit UART
Variable (see text)
SCON.5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set
to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI
will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0.
SCON.4
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
SCON.3
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
SCON.2
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that
was received. In Mode 0, RB8 is not used.
SCON.1
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning
of the stop bit in the other modes, in any serial transmission. Must be cleared by software.
SCON.0
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through
the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by
software.
RI
SU01157
TI
RB8
TB8
REN
SM2
SM1
SM0/FE
0
1
2
3
4
5
6
7
SCON
Reset Value: 00h
Bit Addressable
Address: 98h
Figure 30. Serial Port Control Register (SCON)
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