参数资料
型号: PIC18LF2520-I/SP
厂商: Microchip Technology
文件页数: 29/151页
文件大小: 0K
描述: IC MCU FLASH 16KX16 28-DIP
产品培训模块: Asynchronous Stimulus
标准包装: 15
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 25
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 643 (CN2011-ZH PDF)
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 297
PIC16(L)F1782/3
26.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 26-25).
FIGURE 26-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
26.6.3
WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not idle.
SDA
SCL
SCL deasserted but slave holds
DX
1
DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h
02h
01h
00h (hold off)
03h
02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
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