参数资料
型号: PIC18LF2520-I/SP
厂商: Microchip Technology
文件页数: 77/151页
文件大小: 0K
描述: IC MCU FLASH 16KX16 28-DIP
产品培训模块: Asynchronous Stimulus
标准包装: 15
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 25
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 643 (CN2011-ZH PDF)
PIC16(L)F1782/3
DS41579C-page 344
Preliminary
2011-2012 Microchip Technology Inc.
27.5.2.3
EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
Master Reception”), with the following exceptions:
Sleep
CREN bit is always set, therefore the receiver is
never Idle
SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
27.5.2.4
Synchronous Slave Reception
Set-up:
1.
Set the SYNC and SPEN bits and clear the
CSRC bit.
2.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
3.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4.
If 9-bit reception is desired, set the RX9 bit.
5.
Set the CREN bit to enable reception.
6.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
9.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 27-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON
C2OUTSEL
CC1PSEL
SDOSEL
SCKSEL
SDISEL
TXSEL
RXSEL
CCP2SEL
BAUDCON
ABDOVF
RCIDL
—SCKP
BRG16
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
*
Page provides register information.
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