参数资料
| 型号： | PIC18LF4331T-I/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 63/119页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 4KX16 44QFN |
| 标准包装： | 1,600 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LVD，电源控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 36 |
| 程序存储器容量： | 8KB（4K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 数据转换器： | A/D 9x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-VQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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PIC18F2331/2431/4331/4431
DS39616D-page 48
2010 Microchip Technology Inc.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In most
cases, these bits can only be cleared by the event and
must be set by the application after the event. The state
of these flag bits, taken together, can be read to indicate
the type of Reset that just occurred. This is described in
more detail in Section 5.6 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
. BOR is covered in
.
Note 1:
If the BOREN Configuration bit is set
(Brown-out Reset enabled), the BOR bit
is ‘1’ on a Power-on Reset. After a
Brown-out Reset has occurred, the BOR
bit will be cleared and must be set by
firmware to indicate the occurrence of the
next Brown-out Reset.
2:
It is recommended that the POR bit be
set after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R-1
R/W-0
IPEN
—
—RI
TO
PD
POR(2)
BOR(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN:
Interrupt Priority Enable bit
1
= Enable priority levels on interrupts
0
= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented:
Read as ‘0’
bit 4
RI: RESET
Instruction Flag bit
1
= The RESET instruction was not executed (set by firmware only)
0
= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO:
Watchdog Time-out Flag bit
1
= Set by power-up, CLRWDT instruction or SLEEP instruction
0
= A WDT time-out occurred
bit 2
PD:
Power-Down Detection Flag bit
1
= Set by power-up or by the CLRWDT instruction
0
= Set by execution of the SLEEP instruction
bit 1
POR:
Power-on Reset Status bit(2)
1
= A Power-on Reset has not occurred (set by firmware only)
0
= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR:
Brown-out Reset Status bit(1)
1
= A Brown-out Reset has not occurred (set by firmware only)
0
= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1:
If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2:
The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 5.6 “Reset State of Registers” for additional information.
Note 1:
It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2:
Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
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