参数资料
型号: PIC24HJ128GP306A-E/MR
厂商: Microchip Technology
文件页数: 19/20页
文件大小: 0K
描述: IC PIC MCU FLASH 128KB 64-QFN
标准包装: 40
系列: PIC® 24H
核心处理器: PIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 128KB(43K x 24)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 18x10b/12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 管件
PIC24HJXXXGPX06/X08/X10
DS80280G-page 8
2008 Microchip Technology Inc.
8.
Module: SPI in Slave Select Mode
The
SPI
module
Slave
Select
functionality
(enabled by setting SSEN = 1) will not function
correctly. Whether the SSx pin (x = 1 or 2) is high
or low, the SPI data transfer will be completed and
an interrupt will be generated.
Work around
If DMA is not being used, poll the SSx pin state
using the Change Notification (CN) pin associated
to the SSx pin as follows:
1. Disable the SPIx module by clearing the
SPIEN bit in the SPIxSTAT register.
2. Clear the SSEN bit in the SPIxCON1 register
to allow the I/O port to control the SSx pin.
3. Ensure that the CNx pin is configured as a
digital input by setting the associated bit in the
TRISx register.
4. Enable interrupts for the selected CNx pin by
setting the appropriate bits in the CNEN1 and
CNEN2 registers.
5. Turn on the weak pull-up device for the
selected CNx pins by setting the appropriate
bits in the CNPU1 and CNPU2 registers.
6. Clear the CNIF interrupt flag in the IFSx
register.
7. Select the desired interrupt priority for CNx
interrupts using the CNIP<2:0> control bits in
the IPCx register.
8. Enable CNx interrupts using the CNIE control
bit in the IECx register.
9. In the CNx Interrupt Service Routine, read the
PORTx register associated to the SSx pin:
a) If the PORTx bit is ‘0’, then enable the
SPIx module by setting the SPIEN bit and
perform the required data read/write.
b) If the PORTx bit is ‘1’, then disable the
SPIx module by setting the SPIEN bit,
clear the SPI interrupt flag (SPIxIF),
perform a dummy read of the SPIxBUF
register and return from the Interrupt
Service Routine (ISR).
If DMA is being used, no work around exists.
9.
Module: SPI
The SMP bit (SPIxCON1<9>, where x = 1 or 2)
does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master
mode. In this mode, whether the SMP bit is set or
cleared, the data is always sampled at the end of
data output time.
Work around
If sampling at the middle of data output time is
required, then configure the SPI module to use a
clock prescale factor other than 1:1 using the
PPRE<1:0>
and
SPRE<2:0>
bits
in
the
SPIxCON1 register.
10. Module: ECAN
If multiple ECAN transmit buffers are enabled
(multiple TXREQ or TXEN bits are set to ‘1’
simultaneously), then the message transmissions
from the enabled buffers may interfere with one
another. As a result, incorrect ID and data
transmissions will occur intermittently.
Work around
Enable only Buffer 0 for transmission at any given
time. In the user application, this can be ensured
by checking that all other TXREQn and TXENn
bits are clear, before setting the TXREQn bit or
TXENn to Buffer 0.
11. Module: ECAN
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer SID. If the ECAN module
detects a Start-of-Frame (SOF) in the third bit of
interframe space and if a message to be
transmitted is pending, the first five bits of the
transmitted identifier may be corrupted.
Work around
None.
12. Module: ECAN Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
Work around
Do not use Loopback mode.
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