参数资料
型号: PIC24HJ128GP306A-E/MR
厂商: Microchip Technology
文件页数: 2/20页
文件大小: 0K
描述: IC PIC MCU FLASH 128KB 64-QFN
标准包装: 40
系列: PIC® 24H
核心处理器: PIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 128KB(43K x 24)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 18x10b/12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 管件
PIC24HJXXXGPX06/X08/X10
DS80280G-page 10
2008 Microchip Technology Inc.
22. Module: UART
With the auto-baud feature selected, the sync
break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the sync break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
23. Module: I2C
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL (I2CxSTAT<7>) bit being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN
register
can
be
written,
although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software and I2CxTRN register must be rewritten.
24. Module: I2C
The ACKSTAT bit (I2CxSTAT<15>) only reflects
the
received
ACK/NACK
status
for
Master
transmissions, but not for Slave transmissions. As
a result, a Slave cannot use this bit to determine if
it received an ACK or a NACK from a Master. In
future silicon revisions, the ACKSTAT bit will
reflect received ACK/NACK status for both Master
and Slave transmissions.
Work around
The SDA pin should be connected to any other
available I/O pin on the device. After transmitting a
byte, the Slave should poll the SDA line (subject to
a time-out period dependent on the application) to
determine if an ACK (‘0’) or NACK (‘1’) was
received.
25. Module: I2C
The D_A Status bit (I2CxSTAT<5>) gets set on a
slave data reception in the I2CxRCV register, but
does not get set on a slave write to the I2CxTRN
register. In future silicon revisions, the D_A bit will
get set on a slave write to the I2CxTRN register.
Work around
Use the D_A Status bit only for determining slave
reception status and not slave transmission status.
26. Module: Traps and Idle Mode
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine. Instead, the device will
simply wake-up from Idle mode and continue code
execution if the Fail-Safe Clock Monitor (FSCM) is
enabled.
Work around
Whenever
the
device
wakes
up
from
Idle
(assuming the FSCM is enabled) the user software
should check the state of the OSCFAIL bit
(INTCON1<1>) to determine whether a clock
failure occurred, and then perform the appropriate
clock switch operation.
Regardless, the Trap
Service Routine must be included in the user
application.
27. Module: MCLR Wake-up from Sleep
Mode
If a MCLR reset pulse causes the device to
wake-up from Sleep mode, the device wakes up
without waiting for the on-chip voltage regulator to
power-up. This will subsequently result in a
Brown-out Reset (BOR).
Work around
None.
28. Module: ECAN
The C1RXOVF2 and C2RXOVF2 registers are
non-functional. They are always read back as
0x0000, even when a receive overflow has
occurred.
Work around
None.
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PIC24HJ128GP306A-I/PT 功能描述:16位微控制器 - MCU 16 Bit MCU 40MIPS 128KB FLASH RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT
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