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参数资料
| 型号： | PLL2128X |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz |
| 文件页数： | 10/13页 |
| 文件大小： | 76K |
| 代理商： | PLL2128X |
PLL2128X (PRELIMINARY)
20MHZ ~ 100MHZ FSPLL
6
FUNCTIONAL DESCRIPTION
A PLL is the circuit synchronizing an output signal (generated by a VCO) with a reference or input signal in
frequency as well as in phase. The pll2128x can provide frequency multiplication capabilities, but does not
support functions such as deskew and phase synchronization between Fin and Fout.
PLL2128X consists of the following basic blocks.
— The phase frequency detector (PFD) detects the phase difference between the reference clock and feedback
clock, then generates UP/DOWN error signals. If reference clock leads or lags feedback clock, the charge
pump charges or discharges the following loop filter according to UP/DOWN signal.
— The loop filter suppresses high frequency components in the charge pump voltage (Vctrl), allowing the dc
value to control the VCO frequency.
— The voltage-controlled oscillator generates the clock signal proportional to control voltage.
Required frequency is produced by appropriate selection of dividers P, M and S.
Fout = Fin
× m/(p × s)
m = M+8 , p = P+2 , s = 1, 2, 4, 8
— Don't set the value P or M to all zero, that is 000000/00000000.
— The range of P and M: 1
≤ P ≤ 62, 1 ≤ M ≤ 248
— The M and P must be selected considering stability and VCO range.
VCO output frequency range of pll2128x is from 100MHz to 200MHz.
Digital Data Format:
Main Divider
Pre Divider
Post Scaler
M7, M6, M5, M4, M3, M2, M1, M0
P5, P4, P3, P2, P1, P0
S1, S0
NOTE: M[7] - M[0]: main-divider
1
≤ M ≤ 248
P[5] - P[0]: pre-divider
1
≤ P ≤ 62
S[1] - S[0]: post-scaler
0
≤ S ≤ 3
Important Notice:
Please contact SEC application engineer for proper selection of M, P, S values.
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