PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
7
PIN DIAGRAM
The OCTLIU is packaged in a 288-pin Tape-SBGA package having a body size of 23mm by
23mm.
Figure 7
– Pin Diagram
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
ALE/
LEN4[2]
VSS
D[1]/
LEN6[2]
D[2]/
LEN7[0]
D[4]/
LEN7[2]
VSS
VDD1V8
TAVS2[1]
TXRING2 [1] TXRING1 [1]
TXTIP1[1]
TXTIP2[1]
TXTIP2 [8]
TXTIP1 [8]
TXRING1 [8] TXRING2 [8]
RSTB
LOS
SRCCLK
SRCLK
VDD3V3
TDI
A
B
VDD3V3
VDD3V3
CSB/
LEN5[2]
D[0]/
LEN6[1]
D[3]/
LEN7[1]
D[6]/
LEN8[1]
SBI_EN
QAVS[4]
RES[5]
TAVD3[1]
TAVS3[8]
TAVD2[8]
QAVD[4]
VDD1V8
VDD3V3
RES[1]
RES[6]
SRCDO
SRDO
SRCASC
TDO
HW_ONLY
B
C
A[8]/
LEN3[2]
A[9]/
LEN4[0]
A[10]/
LEN4[1]
RDB/
LEN5[1]
VDD3V3
VDD3V3
VSS
D[7]/
LEN8[2]
CAVD
TAVD2[1]
TAVS3[1]
TAVD3[8]
TAVS2[8]
VSS
VSS
LOS_L1
SRCODE
SRCEN
SREN
VSS
TCK
SBI2CLK
C
D
A[4]/
LEN2[1]
A[5]/
LEN2[2]
A[6]/
LEN3[0]
VSS
WRB/
LEN5[0]
INTB/
LEN6[0]
VSS
D[5]/
LEN8[0]
CAVS
TAVS1[1]
TAVD1[1]
TAVD1[8]
TAVS1[8]
XCLK
RSYNC/
ICLK_OUT
VDD3V3
SRDI
VSS
NC
TMS
VDD3V3
RAVS1[8]
D
E
A[0]/
LEN1[0]
A[1]/
LEN1[1]
A[2]/
LEN1[2]
A[7]/
LEN3[1]
TRSTB
VSS
RAVD2[8]
RAVD2[7]
E
F
RAVS1[1]
RAVD2[1]
QAVD[1]
A[3]/
LEN2[0]
QAVS[3]
RES[4]
RAVS2[7]
TXRING2 [7]
F
G
RAVD1[1]
RXTIP[1]
RAVS2[1]
VDD3V3
RAVS2[8]
RXTIP[8]
RAVS1[7]
TXRING1 [7]
G
H
TXRING2 [2]
RAVD2[2]
RAVS2[2]
RXRING[1]
RXRING [8]
RAVD1[8]
RAVD1[7]
TXTIP1 [7]
H
J
TXRING1 [2]
RXTIP[2]
RAVS1[2]
RXRING [2]
RXRING [7]
RXTIP[7]
TAVS2[7]
TXTIP2 [7]
J
K
TXTIP1[2]
RAVD1[2]
TAVS2[2]
TAVS1[2]
TAVS1[7]
TAVD2[7]
TAVD3[7]
TXTIP2 [6]
K
L
TXTIP2 [2]
TAVD2[2]
TAVD3[2]
TAVD1[2]
Bottom View
TAVD1[7]
TAVS3[7]
TAVS3[6]
TXTIP1[6]
L
M
TXTIP2 [3]
TAVS3[2]
TAVS3[3]
TAVD1[3]
TAVD1[6]
TAVD3[6]
TAVD2[6]
TXRING1 [6]
M
N
TXTIP1 [3]
TAVD3[3]
TAVD2[3]
TAVS1[3]
TAVS1[6]
TAVS2[6]
RAVD1[6]
TXRING2 [6]
N
P
TXRING1 [3]
TAVS2[3]
RAVD1[3]
RXRING [3]
RXRING [6]
RAVS1[6]
RAVD2[6]
RXTIP[6]
P
R
TXRING2 [3]
RXTIP[3]
RAVD2[3]
RXTIP[4]
RXTIP[5]
RXRING [5]
RAVD1[5]
RAVS2[6]
R
T
RAVS1[3]
RAVS2[3]
RAVD1[4]
RAVS2[4]
QAVD[3]
RAVS2[5]
RAVD2[5]
RAVS1[5]
T
U
RXRING [4]
RAVS1[4]
RAVD2[4]
TCLK[1]/
IDATA[1]
TCLK[7]/
IDATA[7]
TDN[8]/
IFP_IN
TDP[8]/
ADATA[7]
VSS
U
V
RES[1]
QAVS[1]
VSS
TDP[2]/
ADATA[1]
TDN[6]/ AV5
TCLK[6]/
IDATA[6]
TDN[7]/
ICLK_IN
TCLK[8]/
IDATA[8]
V
W
TDP[1]/
ADATA[0]
TDN[1]/
REFCLK
TCLK[2]/
IDATA[2]
VDD3V3
TDN[4]/ ADP
VDD3V3
VDD3V3
RDN[3]/
RLCV[3]/
C1FPOUT
VSS
TAVS1[4]
TAVD1[4]
TAVD1[5]
TAVS1[5]
VDD1V8
RDP[5]/
DDATA[4]
RCLK[6]/
EDATA[6]
RCLK[7]/
EDATA[7]
RDP[8]/
DDATA[7]
NC
VDD3V3
TCLK[5]/
IDATA[5]
TDP[7]/
ADATA[6]
W
Y
TDN[2]/
AC1FP
TDP[3]/
ADATA[2]
VDD3V3
TDP[4]/
ADATA[3]
VSS
RDP[2]/
DDATA[1]
RCLK[3]/
EDATA[3]
VDD3V3
RDN[4]/
RLCV[4]/
DDP
TAVS2[4]
TAVD3[4]
TAVS3[5]
TAVD2[5]
RES[3]
RDN[5]/
RLCV[5]/
DPL
VDD3V3
VSS
RDP[7]/
DDATA[6]
RDN[8]/
RLCV[8]/
DACTIVE
VSS
TDP[5]/
ADATA[4]
TDP[6]/
ADATA[5]
Y
AA
TCLK[3]/
IDATA[3]
TDN[3]/
DC1FP
TCLK[4]/
IDATA[4]
RCLK[1]/
EDATA[1]
RCLK[2]/
EDATA[2]
VSS
VSS
RCLK[4]/
EDATA[4]
VDD1V8
QAVD[2]
TAVD2[4]
TAVS3[4]
TAVD3[5]
TAVS2[5]
QAVS[2]
VSS
VSS
RDP[6]/
DDATA[5]
RDN[7]/
RLCV[7]/
ECLK
VDD3V3
VSS
TDN[5]/ APL
AA
AB
VSS
VSS
VSS
RDP[1]/
DDATA[0]
RDN[1]/
RLCV[1]/
IFP_OUT
RDN[2]/
RLCV[2]/
EFP
RDP[3]/
DDATA[2]
RDP[4]/
DDATA[3]
TXRING2 [4] TXRING1 [4]
TXTIP1[4]
TXTIP2 [4]
TXTIP2 [5]
TXTIP1[5]
TXRING1 [5] TXRING2 [5]
RCLK[5]/
EDATA[5]
RDN[6]/
RLCV[6]/
DV5
VDD3V3
VSS
RCLK[8]/
EDATA[8]
VDD3V3
AB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1