PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
20
Pin Name
Type
Pin
No.
Function
SBI to Clk/Data Converter Interface
SBI_EN
SBI2CLK
Input
B16
C1
The SBI interface enable signals (SBI_EN, SBI2CLK) select
between the SBI and serial clock/data system side interfaces and
allow selection of an operating mode in which the LIUs are
disabled and the OCTLIU functions as a converter between the
SBI interface and serial clk/data. The signals select the device
operating mode as follows:
SBI_EN SBI2CLK Mode
0
0
LIUs enabled, clk/data selected on system
side.
1
0
LIUs enabled, SBI interface selected on
system side.
0
1
LIUs disabled, converter mode.
1
1
Unused
IDATA[1]/TCLK[1]
IDATA[2]/TCLK[2]
IDATA[3]/TCLK[3]
IDATA[4]/TCLK[4]
IDATA[5]/TCLK[5]
IDATA[6]/TCLK[6]
IDATA[7]/TCLK[7]
IDATA[8]/TCLK[8]
Input
U19
W20
AA22
AA20
W2
V3
U4
V1
The Ingress Data inputs (IDATA[8:1]) carry eight serial 1.544
Mbps or 2.048 Mbps data streams to be mapped on to the SBI
interface when the device is operating as a SBI to clk/data
converter. The eight serial data streams are sampled on the
rising edge of ICLK_IN.
IDATA[8:1] share the same pins as the TCLK[8:1] inputs.
IDATA[8:1] are selected when SBI2CLK is tied high.
ICLK_IN/TDN[7]
Input
V2
The Ingress Input Clock (ICLK_IN) should be 1.544 MHz for DS1
or 2.048 MHz for E1 data streams and is used to sample the
IDATA[8:1] and IFP_IN signals.
ICLK_IN shares the same pin as the TDN[7] input. ICLK_IN is
selected when SBI_EN or SBI2CLK is tied high.
IFP_IN/TDN[8]
Input
U3
The Ingress Frame Pulse input (IFP_IN) should be set high
during the framing bits of DS1 streams or during the first bit of the
framing octet of E1 data streams. IFP_IN is sampled on the
rising edge of ICLK_IN.
IFP_IN shares the same pin as the TDN[8] input. IFP_IN is
selected when SBI_EN or SBI2CLK is tied high.
ICLK_OUT/RSYNC
Output
D8
The Ingress Output Clock (ICLK_OUT) is a nominal 1.544 MHz
(for DS1) or 2.048 MHz (for E1) clock and may be used as a
source for the ICLK_IN clock if desired.
ICLK_OUT shares the same pin as the RSYNC output.
ICLK_OUT is selected when SBI2CLK is tied high.