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PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
379
dedicated 128 byte FIFO for each tributary. The HDLC transmitter reads the
FIFO once a complete packet is written or when a specified FIFO fill threshold is
passed. Also, Performance Reporting Messages (PRMs) may be transmitted
autonomously once a second. The transmitter takes care of bit stuffing and
insertion of the CRC protection and flags.
By default, the HDLC transmitter operates in a clear channel mode in which the
contents of the FIFO are transmitted verbatim without bit stuffing or CRC. If the
FIFO becomes empty, flags will be transmitted. To enable the HDLC features,
the DELIN context bit must be set via the THDL Indirect Channel Data registers.
FIFO thresholds must be set to avoid overflows and underflows, which result in
lost data and an abort sequence. The actual thresholds depend on operating
system latencies and algorithms used to write the packets. The Upper Transmit
Threshold value determines how many bytes must be written before transmission
of an incomplete packet starts. It should be set at a value large enough to
ensure an underflow does not occur before the complete packet is written under
worst case conditions, such as excessive interrupt servicing. Note that complete
packets are always transmitted regardless of the Upper Transmit Threshold
value. A large Upper Transmit Threshold value may result in FIFO overflows if
large packets are being written. To avoid overflows, it is recommended writes
only resume after the Lower Interrupt Threshold is reached.
The T1/E1 Transmit HDLC processor (THDL) can be used in a polled or interrupt
driven mode for the transfer of packet data. In the polled mode, the processor
controlling the THDL must periodically read the THDL Interrupt Status #1 register
to determine if there’s been a change in FIFO status. In the interrupt driven
mode, the processor controlling the THDL uses the TE-32 INTB output and the
TE-32 Master Interrupt Source registers to determine when to service the THDL.
In the case of interrupt driven data transfer from the processor to THDL, the INTB
output of the TE-32 is connected to the interrupt input of the processor. The
processor interrupt service routine verifies what block generated the interrupt by
reading the TE-32 Master Interrupt Source register followed by the Master
Interrupt Source T1E1 register to determine if HDLC Transmitter is the interrupt
source. Once it has identified that the THDL has generated the interrupt, it
processes the data in the following order:
1.
Read the THDL Interrupt Status #1 register. The value returned will
indicate if any of THDL Interrupt Status #2 through #11 should be read. Any
bits returned as a logic 1 will indicate the associated tributary needs servicing.
The bits in the THDL Interrupt Status registers are write-one-to-clear, so the
value read should be written back. Repeat steps 2 through 8 for each
tributary with an INT bit set.