PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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When Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP ingress
interface multiplexes up to 768 channels from 32 T1s or E1s, up to 768 channel
associated signaling (CAS) channels from 32 T1s or E1s and common channel
signaling (CCS) from up to 32 T1s or E1s. The H-MVIP interfaces use common
clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for
synchronization.
The three ingress H-MVIP interfaces operate independently except that using
any one of these forces the T1 or E1 framer to operate in synchronous mode,
meaning that elastic stores are used.
Eight H-MVIP data signals, MVID[1:8] provide H-MVIP access for up to 768 data
channels. The H-MVIP mapping is fixed such that each group of four nearest
neighbor T1 or E1 links make up the individual 8.192 Mbit/s H-MVIP signal. This
mode is selected when the SYSOPT[1:0] bits in the Global Configuration register
are set to H-MVIP.
A separate H-MVIP interface consisting of eight pins is for access to the channel
associated signaling for all of the 768 data channels. The CAS is time division
multiplexed exactly the same way as the data channels and is synchronized with
the H-MVIP data channels. Over a T1 or E1 multi-frame, the four CAS bits per
channel are repeated with each data byte.
The CAS H-MVIP interface can be used in parallel with the SBI Drop bus as an
alternative method for accessing the CAS bits while data transfer occurs over the
SBI bus. This is selected when the SYSOPT[1:0] bits in the Global Configuration
register are set to “SBI Interface with CAS or CCS H-MVIP Interface”.
A separate H-MVIP interface consisting of three signals is used to time division
multiplex the common channel signaling (CCS) for all T1s and E1s and
additionally the V5 channels in E1 mode. The CCS H-MVIP interface,
CCSID[1:3], is not multiplexed with any other pins. CCSID[1:3] can be used in
parallel with the Clock Slave:H-MVIP mode when SYSOPT[1:0] is set to “H-MVIP
Interface” and any of the CCSEN, CCS16EN, CCS15EN and CCS31EN bits for
the tributary are set to logic 1 through the T1/E1 Transmitter Indirect Channel
Data registers or the SBI Add bus when SYSOPT[1:0] is set to “SBI Interface with
CAS or CCS H-MVIP Interface” and any of the CCSEN, CCS16EN, CCS15EN
and CCS31EN bits for the tributary are set to logic 1 through the T1/E1
Transmitter Indirect Channel Data registers.
The TS0ID output provides the contents of E1 TS0.
When accessing the CAS or CCS signaling via the H-MVIP interface in parallel
with the SBI interface a receive signaling elastic store is used to adapt any timing
differences between the data interface and the CAS or CCS H-MVIP interface.