PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
70
9.12 T1/E1 Pseudo Random Binary Sequence Generation and Detection (PRBS)
The Pseudo Random Binary Sequence Generator/Detector (PRBS) is a software
selectable PRBS generator and checker for 2
7
-1, 2
11
-1, 2
15
-1 or 2
20
-1 PRBS
polynomials for use in the T1 and E1 links. PRBS patterns may be generated
and monitored in both the transmit or receive directions for all T1 and E1 links
simultaneously. The generator is capable of inserting single bit errors under
microprocessor control.
The detector auto-synchronizes to the expected PRBS pattern and accumulates
the total number of bit errors in a 16-bit counter. The error count accumulates
over the interval defined by writes to the Global PMON Update register. When a
transfer is triggered, the holding register is updated, and the counter reset to
begin accumulating for the next interval. The counter is reset in such a way that
no events are missed. The data is then available until the next transfer.
In addition to the basic PRBS generators and receivers associated with each
T1/E1 link, six full featured generator/receiver pairs are available for association
with any software selectable link. Any subset of bits within a frame (except the
T1 F-bit) may be programmed to carry either a pseudo-random or fixed pattern.
The six generators can be programmed to generate any pseudo-random pattern
with length up to 2
32
-1 bits or any user programmable bit pattern from 1 to 32 bits
in length. It also can generate the four DDS codes specified by Bellcore GR-819-
CORE. In addition, the PRGD can insert single bit errors or a bit error rate
between 10-1 to 10-7.
The six receivers can be programmed to check for the generated pseudo random
pattern. The receivers can perform an auto synchronization to the expected
pattern and accumulates the total number of bits received and the total number of
bit errors in two 32-bit counters. The counters accumulate either over intervals
defined by writes to the Pattern Detector registers or upon writes to the Global
PMON Update Register. When a transfer is triggered, the holding registers are
updated, and the counters reset to begin accumulating for the next interval. The
counters are reset in such a way that no events are missed. The data is then
available in the holding registers until the next transfer.
9.13 Egress H-MVIP System Interface
The Egress H-MVIP System Interface (Figure 11) provides system side H-MVIP
access for up to 32 T1 or E1 transmit streams. There are three separate
interfaces for data, CAS signaling and CCS signaling. The H-MVIP signaling
interfaces can be used in combination with the SBI interface in certain
applications. Control of the system side interface is global to TE-32 and is