
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
92
Register 0x010 : FREEDM-32P32 Master Link Activity Monitor
Bit
Type
Function
Default
Bit 31
to
Bit 16
Unused
XXXXH
Bit 15
R
TLGA[7]
X
Bit 14
R
TLGA[6]
X
Bit 13
R
TLGA[5]
X
Bit 12
R
TLGA[4]
X
Bit 11
R
TLGA[3]
X
Bit 10
R
TLGA[2]
X
Bit 9
R
TLGA[1]
X
Bit 8
R
TLGA[0]
X
Bit 7
R
RLGA[7]
X
Bit 6
R
RLGA[6]
X
Bit 5
R
RLGA[5]
X
Bit 4
R
RLGA[4]
X
Bit 3
R
RLGA[3]
X
Bit 2
R
RLGA[2]
X
Bit 1
R
RLGA[1]
X
Bit 0
R
RLGA[0]
X
This register provides activity monitoring on FREEDM-32P32 receive and
transmit link inputs. When a monitored input makes a low to high transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions
is indicated by the corresponding register bit reading low. This register should be
read at periodically to detect for stuck at conditions.
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not