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参数资料
| 型号： | PowerPC 405CR |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 23/42页 |
| 文件大小： | 565K |
| 代理商： | POWERPC 405CR |
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PowerPC 405CR Embedded Controller Data Sheet
23
Pin Lists
The PPC405CR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA).
The following tables describe the package level pinout.
In the table “Signal Functional Description” on page 24, each I/O signal is listed along with a short description
of the signal function. Some signals are multiplexed onto the same pin (ball) so that the pin is usable for
different functions. Multiplexed signals are shown in square brackets following the default signal (for example,
C0:3[BE0:3]) and described consecutively within each pin functional description. Active-low signals such as
BE0:3 are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
In addition to multiplexing, many pins are also multi-purpose. These pins are described in the table using a
single row with a text description that indicates the different functional uses of the pin. For example, the EBC
peripheral controller address pins are used as outputs by the PPC405CR to broadcast an address to external
slave devices when the PPC405CR has control of the external bus. When during the course of normal chip
operation an external master gains ownership of the external bus, these same pins are used as inputs which
are driven by the external master and received by the EBC in the PPC405CR.
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 39). Note
that these are
not multiplexed
pins since the function of the pins is not programmable.
The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned.
Pin Summary
Group
No. of Pins
SDRAM
71
External Peripheral
97
External Master
9
Internal Peripheral
15
Interrupts
7
JTAG
5
System
18
Total Signal Pins
222
AV
DD
OV
DD
V
DD
Gnd
1
16
16
40
Thermal (and Gnd)
16
Reserved
5
Total Pins
316
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