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参数资料
| 型号： | PowerPC 405CR |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 39/42页 |
| 文件大小： | 565K |
| 代理商： | POWERPC 405CR |
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PowerPC 405CR Embedded Controller Data Sheet
39
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to PPC405CR start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during
reset. They are used for other signals during normal operation. The following table lists the strapping pins
along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
PLL Tuning
for 6
≤
M
≤
7 use choice 3
for 7 < M
≤
12 use choice 5
for 12 < M
≤
32 use choice 6
See Note.
W15
U13
V20
Choice 1; TUNE[5:0] = 010001
0
0
0
Choice 2; TUNE[5:0] = 010010
0
0
1
Choice 3; TUNE[5:0] = 010011
0
1
0
Choice 4; TUNE[5:0] = 010100
0
1
1
Choice 5; TUNE[5:0] = 010101
1
0
0
Choice 6; TUNE[5:0] = 010110
1
0
1
Choice 7; TUNE[5:0] = 010111
1
1
0
Choice 8; TUNE[5:0] = 100100
1
1
1
PLL Forward Divider
C16
B17
Bypass mode
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 6
1
1
PLL Feedback Divider
B16
A14
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
PLB Divider from CPU
B18
D16
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
OPB Divider from PLB
T4
U5
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
External Bus Divider from PLB
C17
P18
Divide by 2
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 5
1
1
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