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参数资料
| 型号： | PowerPC 405CR |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 37/42页 |
| 文件大小： | 565K |
| 代理商： | POWERPC 405CR |
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PowerPC 405CR Embedded Controller Data Sheet
37
I/O Specifications—200MHz
Notes:
1.
The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
2.
SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and rising-
edge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
3. SDRAM CLK0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a typical clock
network or a lumped 10pF load.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50pF load
I/O H
(maximum)
I/O L
(minimum)
SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemClkOut0:1
MemData0:31
RAS
WE
External SLAVE Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3[TC0:3]
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External MASTER Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
n/a
n/a
n/a
n/a
n/a
n/a
2
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
n/a
n/a
1
n/a
n/a
7.3
5.8
7.3
4.7
6.2
6
6
7.8
0
6.2
7.4
7.4
1
1
1
1
1
1
1
1
-1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
12
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
1, 2
2
1, 2
2
2
2
2
1, 2
2, 3
2
1, 2
1, 2
n/a
dc
dc
4
4
n/a
dc
dc
1
1
8
0
12
n/a
12
19
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
9
10
8
n/a
0
0
0
n/a
8
12
8
n/a
n/a
9
0
12
8
PerClk
6
1
10
8
10.5
8
n/a
8
0
0
0
0
19
12
19
12
n/a
12
12
8
12
8
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
4
5
9
4
n/a
1
1
1
1
n/a
0
n/a
n/a
6
n/a
n/a
4
6
n/a
4
n/a
n/a
1
n/a
n/a
1
1
n/a
1
8
8
0
0
12
12
n/a
19
12
n/a
n/a
19
n/a
8
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
n/a
8
8
n/a
n/a
0.9
n/a
n/a
0
0
n/a
n/a
0.9
n/a
n/a
12
8
n/a
n/a
12
n/a
4
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