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参数资料
| 型号： | PowerPC 405CR |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 28/42页 |
| 文件大小： | 565K |
| 代理商： | POWERPC 405CR |
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PowerPC 405CR Embedded Controller Data Sheet
28
System Interface
SysClk
Main system clock input
I
5V tolerant
3.3V LVTTL
Rcvr
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to start a system reset. The
PPC405CR then holds the output low for 8192 cycles to reset all
internal and external logic connected to SysReset. A system
reset can also be initiated by software.
I/O
5V tolerant
3.3V LVTTL
Rcvr
1, 2
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status.To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1 (A22, AF18),
6 (AF18 only)
GPIO5:8[TS3:6]
General Purpose I/O
Trace status. To access this function, software must toggle a
DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
GPIO9[TrcClk]]
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
TestEn
Test Enable
I
5V tolerant
Rcvr w/ PD
3
RcvrInh
Receiver Inhibit. Set to 1 for normal operation. Setting to 0
disables all inputs for test purposes.
I
5V tolerant
Rcvr
2
DrvrInh1:2
Driver Inhibit 1 and 2. Set to 1 for normal operation. Setting to 0
disables all outputs for test purposes.
I
5V tolerant
Rcvr
2
TmrClk
This input must toggle at a rate of less than one half the CPU
core frequency (less than 100MHz in most cases). In most cases
this input toggles much slower (in the 1MHz to 10MHz range).
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
Signal Functional Description
(Part 5 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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