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| 型号： | PowerPC 750CX |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精简指令集微处理器) |
| 中文描述： | 32位精简指令集计算机（RISC）微处理器（32位精简指令集微处理器） |
| 文件页数： | 17/44页 |
| 文件大小： | 562K |
| 代理商： | POWERPC 750CX |
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PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 17
Figure 4 provides the mode select input timing diagram for the PowerPC 750CX.
5.4
60X Bus Output AC Specifications
Table 8 provides the 60X bus output AC timing specifications for the PowerPC 750CX as defined in Figure 6 on
page 19.
Figure 4. Mode Select Input Timing Diagram
Table 8: 60X Bus Output AC Timing Specifications
1,4,6,7
See Table 2 on page 12 for operating conditions.
Num
Characteristic
1.8V Mode
2.5V Mode
Unit
Notes
Min.
Max.
Min.
Max.
12
SYSCLK to Output Driven (Output Enable Time)
0.3
0.3
ns
13
SYSCLK to Output Valid
–
2.31
–
2.61
ns
14
SYSCLK to Output Invalid (Output Hold)
0.400
0.400
ns
2
15
SYSCLK to Output High Impedance (all signals except ARTRY)
–
2.5
–
2.5
ns
16
SYSCLK to ARTRY high impedance before precharge
–
3.0
–
3.0
ns
17
SYSCLK to ARTRY precharge enable
0.2
×
t
+ 1.0
0.2
×
t
+ 1.0
ns
2, 3, 5
18
Maximum delay to ARTRY precharge
1
1
t
SYSCLK
3, 5
19
SYSCLK to ARTRY high impedance after precharge
2
2
t
SYSCLK
3, 5
Note:
1. All output specifications are measured from the midpoint voltage (0.8V) of the rising edge of SYSCLK to the midpoint voltage of the signal in question
defined in figure 5. Both input and output timings are measured at the pin. Timings are determined by design.
2. This minimum parameter assumes CL = 0pF.
3. t
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
4. Output signal transitions are defined in figure 5.
5. Nominal precharge width for ARTRY is 1.0 t
SYSCLK
.
6. Guaranteed by design and characterization, and not tested.
7. These timings are valid for processors up to 466MHz. 500MHz processor timing behavior and characterization are being evaluated at this time.
V
IH
V
IH
= 1.24V
MODE PINS
10c
11b
HRESET
10c
11b
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