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参数资料
| 型号： | PowerPC 750CX |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精简指令集微处理器) |
| 中文描述： | 32位精简指令集计算机（RISC）微处理器（32位精简指令集微处理器） |
| 文件页数： | 9/44页 |
| 文件大小： | 562K |
| 代理商： | POWERPC 750CX |
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PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 9
3.0 Features
This section summarizes the features of the PowerPC 750CX’s implementation of the PowerPC architecture. Major fea-
tures of the PowerPC 750CX are as follows.
Branch processing unit
- Four instructions fetched per clock
- One branch processed per cycle (plus resolving 2 speculations)
- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
- 512-entry branch history table (BHT) for dynamic prediction
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots
Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units)
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point
unit 2, or floating-point)
- 4-stage pipeline: fetch, dispatch, execute, and complete
- Serialization control (predispatch, postdispatch, execution, serialization)
Decode
- Register file access
- Forwarding control
- Partial instruction decode
Load/store unit
- One cycle load or store cache access (byte, half-word, word, double-word)
- Effective address generation
- Hits under misses (one outstanding miss)
- Single-cycle misaligned access within double word boundary
- Alignment, zero padding, sign extend for integer register file
- Floating-point internal format conversion (alignment, normalization)
- Sequencing for load/store multiples and string operations
- Store gathering
- Cache and TLB instructions
- Big and little-endian byte addressing supported
- Misaligned little-endian support in hardware
Fixed-point units
- Fixed-point unit 1 (FXU1); multiply, divide, shift, rotate, arithmetic, logical
- Fixed-point unit 2 (FXU2); shift, rotate, arithmetic, logical
- Single-cycle arithmetic, shift, rotate, logical
- Multiply and divide support (multi-cycle)
- Early out multiply
- Thirty-two, 32-bit general purpose registers
- Secondary FXU executes integer add/compare instructions
Floating-point unit
- Support for IEEE-754 standard single and double-precision floating-point arithmetic
- Optimized for single-precision multiply/add
- Thirty-two, 64-bit floating point registers
- Enhanced reciprocal estimates
- 3-cycle latency, 1-cycle throughput, single-precision multiply-add
- 3-cycle latency, 1-cycle throughput, double-precision add
- 4-cycle latency, 2-cycle throughput, double-precision multiply-add
相关PDF资料 |
PDF描述 |
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