参数资料
型号: PPC5604BCLL48
厂商: Freescale Semiconductor
文件页数: 54/109页
文件大小: 0K
描述: MCU 32BIT 512K 48MHZ
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z0h
芯体尺寸: 32-位
速度: 48MHz
连通性: CAN,I²C,LIN,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 79
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 16
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 28x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
Package pinouts and signal descriptions
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Freescale Semiconductor
49
HV—High voltage external power supply for voltage regulator module. This must be provided externally through
VDD_HV power pin.
BV—High voltage external power supply for internal ballast module. This must be provided externally through
VDD_BV power pin. Voltage values should be aligned with VDD.
LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
Figure 10. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
The internal voltage regulator requires a controlled slew rate of both VDD_HV and VDD_BV as described in Figure 11.
C
REG
1
(L
V_COR/L
V
_DFLA
)
DEVICE
VSS_LV
VDD_BV
VDD_LV
C
DE
C
1
(B
alla
st
decoup
ling)
VSS_LV
VDD_LV
VDD_HV
VSS_LV
VDD_LV
CREG2 (LV_COR/LV_CFLA)
CREG3
CDEC2
DEVICE
VDD_BV
I
VDD_LVn
VREF
VDD_HV
Voltage Regulator
VSS_HV
VSS_LVn
(supply/IO decoupling)
(LV_COR/LV_PLL)
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