参数资料
型号: PPC5604BCLL48
厂商: Freescale Semiconductor
文件页数: 87/109页
文件大小: 0K
描述: MCU 32BIT 512K 48MHZ
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z0h
芯体尺寸: 32-位
速度: 48MHz
连通性: CAN,I²C,LIN,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 79
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 16
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 28x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
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MPC5
604B
/C
Mic
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Da
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11
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Se
mi
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79
10
tHI
SR D Data hold time for inputs
Master mode
0
0
ns
Slave mode
26
——
——
11
tSUO7
CC D Data valid after SCK edge Master mode
32
50
ns
Slave mode
52
160
12
tHO7
CC D Data hold time for outputs Master mode
0
0
ns
Slave mode
8
13
1 Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4 The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than
tCSC to ensure positive tCSCext.
5 The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than
tASC to ensure positive tASCext.
6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.
7 SCK and SOUT configured as MEDIUM pad
Table 46. DSPI characteristics1 (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1
DSPI2
Unit
Min
Typ
Max
Min
Typ
Max
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